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radeonsi/gfx10: add NGG registers to si_init_config

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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Nicolai Hähnle 2017-11-18 14:32:59 +01:00 • committed by Marek Olšák
parent ae00cae0b7
commit d0c204a1e0
1 changed files with 15 additions and 0 deletions
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15
src/gallium/drivers/radeonsi/si_state.c
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@ -5539,6 +5539,21 @@ static void si_init_config(struct si_context *sctx)
S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
}
if (sctx->chip_class >= GFX10) {
/* Break up a pixel wave if it contains deallocs for more than
* half the parameter cache.
*
* To avoid a deadlock where pixel waves aren't launched
* because they're waiting for more pixels while the frontend
* is stuck waiting for PC space, the maximum allowed value is
* the size of the PC minus the largest possible allocation for
* a single primitive shader subgroup.
*/
si_pm4_set_reg(pm4, R_028C50_PA_SC_NGG_MODE_CNTL,
S_028C50_MAX_DEALLOCS_IN_WAVE(512));
si_pm4_set_reg(pm4, R_028838_PA_CL_NGG_CNTL, 0); /* TODO edge flags? */
}
if (sctx->chip_class >= GFX8) {
unsigned vgt_tess_distribution;