mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-18 20:18:06 +02:00
NV fp parser: Support instruction and TEMP / OUTPUT sizes
Adds support for declaring TEMP and OUTPUT variables as 'LONG' or
'SHORT' precision. The precision specifiers are parsed, but they are
currently ignored. Some support for this may be added in the future,
but neither Intel hardware nor, as far as I'm aware, Radeon hardware
support multiple precisions.
Also adds support for instruction precision ('X', 'H', and 'R')
suffixes and instruction condition code output ('C') suffix. This
results in a fairly major change to the lexer. Instructions are
matched with all the possible suffix strings. The suffix string are
then carved off by a context (i.e., which program mode and options are
set) aware parser that converts the suffixes to bits in
prog_instruction.
This could have been handled in the same way _SAT was originally
handled in the lexer, but it would have resulted in a very large lexer
with lots of opportunity for cut-and-paste errors.
This commit is contained in:
Ian Romanick
parent
9ea4319744
commit
d0adebb8d5
6 changed files with 1418 additions and 1461 deletions
File diff suppressed because it is too large
Load diff
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@ -55,11 +55,13 @@
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} while (0)
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#define return_opcode(condition, token, opcode, sat) \
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#define return_opcode(condition, token, opcode, len) \
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do { \
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if (condition) { \
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if (condition && \
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_mesa_parse_instruction_suffix(yyextra, \
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yytext + len, \
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& yylval->temp_inst)) { \
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yylval->temp_inst.Opcode = OPCODE_ ## opcode; \
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yylval->temp_inst.SaturateMode = SATURATE_ ## sat; \
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return token; \
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} else { \
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yylval->string = strdup(yytext); \
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@ -132,6 +134,11 @@ exp [Ee][-+]?[0-9]+
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frac "."[0-9]+
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dot "."[ \t]*
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sz [HRX]?
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szf [HR]?
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cc C?
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sat (_SAT)?
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%option bison-bridge bison-locations reentrant noyywrap
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%%
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@ -149,121 +156,72 @@ OUTPUT { return OUTPUT; }
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PARAM { return PARAM; }
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TEMP { yylval->integer = at_temp; return TEMP; }
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ABS { return_opcode( 1, VECTOR_OP, ABS, OFF); }
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ABS_SAT { return_opcode(require_ARB_fp, VECTOR_OP, ABS, ZERO_ONE); }
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ADD { return_opcode( 1, BIN_OP, ADD, OFF); }
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ADD_SAT { return_opcode(require_ARB_fp, BIN_OP, ADD, ZERO_ONE); }
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ARL { return_opcode(require_ARB_vp, ARL, ARL, OFF); }
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ABS{sz}{cc}{sat} { return_opcode( 1, VECTOR_OP, ABS, 3); }
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ADD{sz}{cc}{sat} { return_opcode( 1, BIN_OP, ADD, 3); }
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ARL { return_opcode(require_ARB_vp, ARL, ARL, 3); }
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CMP { return_opcode(require_ARB_fp, TRI_OP, CMP, OFF); }
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CMP_SAT { return_opcode(require_ARB_fp, TRI_OP, CMP, ZERO_ONE); }
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COS { return_opcode(require_ARB_fp, SCALAR_OP, COS, OFF); }
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COS_SAT { return_opcode(require_ARB_fp, SCALAR_OP, COS, ZERO_ONE); }
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CMP{sat} { return_opcode(require_ARB_fp, TRI_OP, CMP, 3); }
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COS{szf}{cc}{sat} { return_opcode(require_ARB_fp, SCALAR_OP, COS, 3); }
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DDX { return_opcode(require_NV_fp, VECTOR_OP, DDX, OFF); }
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DDX_SAT { return_opcode(require_NV_fp, VECTOR_OP, DDX, ZERO_ONE); }
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DDY { return_opcode(require_NV_fp, VECTOR_OP, DDY, OFF); }
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DDY_SAT { return_opcode(require_NV_fp, VECTOR_OP, DDY, ZERO_ONE); }
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DP3 { return_opcode( 1, BIN_OP, DP3, OFF); }
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DP3_SAT { return_opcode(require_ARB_fp, BIN_OP, DP3, ZERO_ONE); }
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DP4 { return_opcode( 1, BIN_OP, DP4, OFF); }
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DP4_SAT { return_opcode(require_ARB_fp, BIN_OP, DP4, ZERO_ONE); }
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DPH { return_opcode( 1, BIN_OP, DPH, OFF); }
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DPH_SAT { return_opcode(require_ARB_fp, BIN_OP, DPH, ZERO_ONE); }
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DST { return_opcode( 1, BIN_OP, DST, OFF); }
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DST_SAT { return_opcode(require_ARB_fp, BIN_OP, DST, ZERO_ONE); }
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DDX{szf}{cc}{sat} { return_opcode(require_NV_fp, VECTOR_OP, DDX, 3); }
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DDY{szf}{cc}{sat} { return_opcode(require_NV_fp, VECTOR_OP, DDY, 3); }
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DP3{sz}{cc}{sat} { return_opcode( 1, BIN_OP, DP3, 3); }
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DP4{sz}{cc}{sat} { return_opcode( 1, BIN_OP, DP4, 3); }
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DPH{sz}{cc}{sat} { return_opcode( 1, BIN_OP, DPH, 3); }
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DST{szf}{cc}{sat} { return_opcode( 1, BIN_OP, DST, 3); }
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EX2 { return_opcode( 1, SCALAR_OP, EX2, OFF); }
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EX2_SAT { return_opcode(require_ARB_fp, SCALAR_OP, EX2, ZERO_ONE); }
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EXP { return_opcode(require_ARB_vp, SCALAR_OP, EXP, OFF); }
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EX2{szf}{cc}{sat} { return_opcode( 1, SCALAR_OP, EX2, 3); }
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EXP { return_opcode(require_ARB_vp, SCALAR_OP, EXP, 3); }
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FLR { return_opcode( 1, VECTOR_OP, FLR, OFF); }
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FLR_SAT { return_opcode(require_ARB_fp, VECTOR_OP, FLR, ZERO_ONE); }
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FRC { return_opcode( 1, VECTOR_OP, FRC, OFF); }
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FRC_SAT { return_opcode(require_ARB_fp, VECTOR_OP, FRC, ZERO_ONE); }
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FLR{sz}{cc}{sat} { return_opcode( 1, VECTOR_OP, FLR, 3); }
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FRC{sz}{cc}{sat} { return_opcode( 1, VECTOR_OP, FRC, 3); }
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KIL { return_opcode(require_ARB_fp, KIL, KIL, OFF); }
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KIL { return_opcode(require_ARB_fp, KIL, KIL, 3); }
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LIT { return_opcode( 1, VECTOR_OP, LIT, OFF); }
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LIT_SAT { return_opcode(require_ARB_fp, VECTOR_OP, LIT, ZERO_ONE); }
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LG2 { return_opcode( 1, SCALAR_OP, LG2, OFF); }
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LG2_SAT { return_opcode(require_ARB_fp, SCALAR_OP, LG2, ZERO_ONE); }
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LOG { return_opcode(require_ARB_vp, SCALAR_OP, LOG, OFF); }
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LRP { return_opcode(require_ARB_fp, TRI_OP, LRP, OFF); }
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LRP_SAT { return_opcode(require_ARB_fp, TRI_OP, LRP, ZERO_ONE); }
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LIT{szf}{cc}{sat} { return_opcode( 1, VECTOR_OP, LIT, 3); }
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LG2{szf}{cc}{sat} { return_opcode( 1, SCALAR_OP, LG2, 3); }
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LOG { return_opcode(require_ARB_vp, SCALAR_OP, LOG, 3); }
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LRP{sz}{cc}{sat} { return_opcode(require_ARB_fp, TRI_OP, LRP, 3); }
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MAD { return_opcode( 1, TRI_OP, MAD, OFF); }
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MAD_SAT { return_opcode(require_ARB_fp, TRI_OP, MAD, ZERO_ONE); }
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MAX { return_opcode( 1, BIN_OP, MAX, OFF); }
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MAX_SAT { return_opcode(require_ARB_fp, BIN_OP, MAX, ZERO_ONE); }
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MIN { return_opcode( 1, BIN_OP, MIN, OFF); }
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MIN_SAT { return_opcode(require_ARB_fp, BIN_OP, MIN, ZERO_ONE); }
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MOV { return_opcode( 1, VECTOR_OP, MOV, OFF); }
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MOV_SAT { return_opcode(require_ARB_fp, VECTOR_OP, MOV, ZERO_ONE); }
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MUL { return_opcode( 1, BIN_OP, MUL, OFF); }
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MUL_SAT { return_opcode(require_ARB_fp, BIN_OP, MUL, ZERO_ONE); }
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MAD{sz}{cc}{sat} { return_opcode( 1, TRI_OP, MAD, 3); }
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MAX{sz}{cc}{sat} { return_opcode( 1, BIN_OP, MAX, 3); }
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MIN{sz}{cc}{sat} { return_opcode( 1, BIN_OP, MIN, 3); }
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MOV{sz}{cc}{sat} { return_opcode( 1, VECTOR_OP, MOV, 3); }
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MUL{sz}{cc}{sat} { return_opcode( 1, BIN_OP, MUL, 3); }
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PK2H { return_opcode(require_NV_fp, VECTOR_OP, PK2H, OFF); }
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PK2H_SAT { return_opcode(require_NV_fp, VECTOR_OP, PK2H, ZERO_ONE); }
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PK2US { return_opcode(require_NV_fp, VECTOR_OP, PK2US, OFF); }
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PK2US_SAT { return_opcode(require_NV_fp, VECTOR_OP, PK2US, ZERO_ONE); }
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PK4B { return_opcode(require_NV_fp, VECTOR_OP, PK4B, OFF); }
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PK4B_SAT { return_opcode(require_NV_fp, VECTOR_OP, PK4B, ZERO_ONE); }
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PK4UB { return_opcode(require_NV_fp, VECTOR_OP, PK4UB, OFF); }
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PK4UB_SAT { return_opcode(require_NV_fp, VECTOR_OP, PK4UB, ZERO_ONE); }
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POW { return_opcode( 1, BINSC_OP, POW, OFF); }
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POW_SAT { return_opcode(require_ARB_fp, BINSC_OP, POW, ZERO_ONE); }
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PK2H { return_opcode(require_NV_fp, VECTOR_OP, PK2H, 4); }
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PK2US { return_opcode(require_NV_fp, VECTOR_OP, PK2US, 5); }
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PK4B { return_opcode(require_NV_fp, VECTOR_OP, PK4B, 4); }
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PK4UB { return_opcode(require_NV_fp, VECTOR_OP, PK4UB, 5); }
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POW{szf}{cc}{sat} { return_opcode( 1, BINSC_OP, POW, 3); }
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RCP { return_opcode( 1, SCALAR_OP, RCP, OFF); }
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RCP_SAT { return_opcode(require_ARB_fp, SCALAR_OP, RCP, ZERO_ONE); }
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RFL { return_opcode(require_NV_fp, BIN_OP, RFL, OFF); }
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RFL_SAT { return_opcode(require_NV_fp, BIN_OP, RFL, ZERO_ONE); }
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RSQ { return_opcode( 1, SCALAR_OP, RSQ, OFF); }
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RSQ_SAT { return_opcode(require_ARB_fp, SCALAR_OP, RSQ, ZERO_ONE); }
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RCP{szf}{cc}{sat} { return_opcode( 1, SCALAR_OP, RCP, 3); }
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RFL{szf}{cc}{sat} { return_opcode(require_NV_fp, BIN_OP, RFL, 3); }
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RSQ{szf}{cc}{sat} { return_opcode( 1, SCALAR_OP, RSQ, 3); }
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SCS { return_opcode(require_ARB_fp, SCALAR_OP, SCS, OFF); }
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SCS_SAT { return_opcode(require_ARB_fp, SCALAR_OP, SCS, ZERO_ONE); }
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SEQ { return_opcode(require_NV_fp, BIN_OP, SEQ, OFF); }
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SEQ_SAT { return_opcode(require_NV_fp, BIN_OP, SEQ, ZERO_ONE); }
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SFL { return_opcode(require_NV_fp, BIN_OP, SFL, OFF); }
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SFL_SAT { return_opcode(require_NV_fp, BIN_OP, SFL, ZERO_ONE); }
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SGE { return_opcode( 1, BIN_OP, SGE, OFF); }
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SGE_SAT { return_opcode(require_ARB_fp, BIN_OP, SGE, ZERO_ONE); }
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SGT { return_opcode(require_NV_fp, BIN_OP, SGT, OFF); }
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SGT_SAT { return_opcode(require_NV_fp, BIN_OP, SGT, ZERO_ONE); }
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SIN { return_opcode(require_ARB_fp, SCALAR_OP, SIN, OFF); }
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SIN_SAT { return_opcode(require_ARB_fp, SCALAR_OP, SIN, ZERO_ONE); }
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SLE { return_opcode(require_NV_fp, BIN_OP, SLE, OFF); }
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SLE_SAT { return_opcode(require_NV_fp, BIN_OP, SLE, ZERO_ONE); }
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SLT { return_opcode( 1, BIN_OP, SLT, OFF); }
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SLT_SAT { return_opcode(require_ARB_fp, BIN_OP, SLT, ZERO_ONE); }
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SNE { return_opcode(require_NV_fp, BIN_OP, SNE, OFF); }
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SNE_SAT { return_opcode(require_NV_fp, BIN_OP, SNE, ZERO_ONE); }
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STR { return_opcode(require_NV_fp, BIN_OP, STR, OFF); }
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STR_SAT { return_opcode(require_NV_fp, BIN_OP, STR, ZERO_ONE); }
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SUB { return_opcode( 1, BIN_OP, SUB, OFF); }
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SUB_SAT { return_opcode(require_ARB_fp, BIN_OP, SUB, ZERO_ONE); }
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SWZ { return_opcode( 1, SWZ, SWZ, OFF); }
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SWZ_SAT { return_opcode(require_ARB_fp, SWZ, SWZ, ZERO_ONE); }
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SCS{sat} { return_opcode(require_ARB_fp, SCALAR_OP, SCS, 3); }
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SEQ{sz}{cc}{sat} { return_opcode(require_NV_fp, BIN_OP, SEQ, 3); }
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SFL{sz}{cc}{sat} { return_opcode(require_NV_fp, BIN_OP, SFL, 3); }
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SGE{sz}{cc}{sat} { return_opcode( 1, BIN_OP, SGE, 3); }
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SGT{sz}{cc}{sat} { return_opcode(require_NV_fp, BIN_OP, SGT, 3); }
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SIN{szf}{cc}{sat} { return_opcode(require_ARB_fp, SCALAR_OP, SIN, 3); }
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SLE{sz}{cc}{sat} { return_opcode(require_NV_fp, BIN_OP, SLE, 3); }
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SLT{sz}{cc}{sat} { return_opcode( 1, BIN_OP, SLT, 3); }
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SNE{sz}{cc}{sat} { return_opcode(require_NV_fp, BIN_OP, SNE, 3); }
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STR{sz}{cc}{sat} { return_opcode(require_NV_fp, BIN_OP, STR, 3); }
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SUB{sz}{cc}{sat} { return_opcode( 1, BIN_OP, SUB, 3); }
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SWZ{sat} { return_opcode( 1, SWZ, SWZ, 3); }
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TEX { return_opcode(require_ARB_fp, SAMPLE_OP, TEX, OFF); }
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TEX_SAT { return_opcode(require_ARB_fp, SAMPLE_OP, TEX, ZERO_ONE); }
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TXB { return_opcode(require_ARB_fp, SAMPLE_OP, TXB, OFF); }
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TXB_SAT { return_opcode(require_ARB_fp, SAMPLE_OP, TXB, ZERO_ONE); }
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TXD { return_opcode(require_NV_fp, TXD_OP, TXD, OFF); }
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TXD_SAT { return_opcode(require_NV_fp, TXD_OP, TXD, ZERO_ONE); }
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TXP { return_opcode(require_ARB_fp, SAMPLE_OP, TXP, OFF); }
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TXP_SAT { return_opcode(require_ARB_fp, SAMPLE_OP, TXP, ZERO_ONE); }
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TEX{cc}{sat} { return_opcode(require_ARB_fp, SAMPLE_OP, TEX, 3); }
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TXB{cc}{sat} { return_opcode(require_ARB_fp, SAMPLE_OP, TXB, 3); }
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TXD{cc}{sat} { return_opcode(require_NV_fp, TXD_OP, TXD, 3); }
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TXP{cc}{sat} { return_opcode(require_ARB_fp, SAMPLE_OP, TXP, 3); }
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UP2H { return_opcode(require_NV_fp, SCALAR_OP, UP2H, OFF); }
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UP2H_SAT { return_opcode(require_NV_fp, SCALAR_OP, UP2H, ZERO_ONE); }
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UP2US { return_opcode(require_NV_fp, SCALAR_OP, UP2US, OFF); }
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UP2US_SAT { return_opcode(require_NV_fp, SCALAR_OP, UP2US, ZERO_ONE); }
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UP2H{cc}{sat} { return_opcode(require_NV_fp, SCALAR_OP, UP2H, 4); }
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UP2US{cc}{sat} { return_opcode(require_NV_fp, SCALAR_OP, UP2US, 5); }
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X2D { return_opcode(require_NV_fp, TRI_OP, X2D, OFF); }
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X2D_SAT { return_opcode(require_NV_fp, TRI_OP, X2D, ZERO_ONE); }
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XPD { return_opcode( 1, BIN_OP, XPD, OFF); }
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XPD_SAT { return_opcode(require_ARB_fp, BIN_OP, XPD, ZERO_ONE); }
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X2D{szf}{cc}{sat} { return_opcode(require_NV_fp, TRI_OP, X2D, 3); }
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XPD{sat} { return_opcode( 1, BIN_OP, XPD, 3); }
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vertex { return_token_or_IDENTIFIER(require_ARB_vp, VERTEX); }
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fragment { return_token_or_IDENTIFIER(require_ARB_fp, FRAGMENT); }
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File diff suppressed because it is too large
Load diff
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@ -1811,7 +1811,46 @@ optionalSign: '+' { $$ = FALSE; }
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| { $$ = FALSE; }
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;
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TEMP_statement: TEMP { $<integer>$ = $1; } varNameList
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TEMP_statement: optVarSize TEMP { $<integer>$ = $2; } varNameList
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;
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optVarSize: IDENTIFIER
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{
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/* NV_fragment_program_option defines the size qualifiers in a
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* fairly broken way. "SHORT" or "LONG" can optionally be used
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* before TEMP or OUTPUT. However, neither is a reserved word!
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* This means that we have to parse it as an identifier, then check
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* to make sure it's one of the valid values. *sigh*
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*
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* In addition, the grammar in the extension spec does *not* allow
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* the size specifier to be optional, but all known implementations
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* do.
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*/
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if (!state->option.NV_fragment) {
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yyerror(& @1, state, "unexpected IDENTIFIER");
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YYERROR;
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}
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if (strcmp("SHORT", $1) == 0) {
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} else if (strcmp("LONG", $1) == 0) {
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} else {
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char *const err_str =
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make_error_string("invalid storage size specifier \"%s\"",
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$1);
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yyerror(& @1, state, (err_str != NULL)
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? err_str : "invalid storage size specifier");
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if (err_str != NULL) {
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_mesa_free(err_str);
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}
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YYERROR;
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}
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}
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{
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}
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;
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ADDRESS_statement: ADDRESS { $<integer>$ = $1; } varNameList
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@ -1831,15 +1870,15 @@ varNameList: varNameList ',' IDENTIFIER
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}
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;
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OUTPUT_statement: OUTPUT IDENTIFIER '=' resultBinding
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OUTPUT_statement: optVarSize OUTPUT IDENTIFIER '=' resultBinding
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{
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struct asm_symbol *const s =
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declare_variable(state, $2, at_output, & @2);
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declare_variable(state, $3, at_output, & @3);
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if (s == NULL) {
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YYERROR;
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} else {
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s->output_binding = $4;
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s->output_binding = $5;
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}
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}
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;
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@ -2096,7 +2135,10 @@ asm_instruction_copy_ctor(const struct prog_instruction *base,
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if (inst) {
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_mesa_init_instructions(& inst->Base, 1);
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inst->Base.Opcode = base->Opcode;
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inst->Base.CondUpdate = base->CondUpdate;
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inst->Base.CondDst = base->CondDst;
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inst->Base.SaturateMode = base->SaturateMode;
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inst->Base.Precision = base->Precision;
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asm_instruction_set_operands(inst, dst, src0, src1, src2);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -33,6 +33,67 @@
|
|||
* \author Ian Romanick <ian.d.romanick@intel.com>
|
||||
*/
|
||||
|
||||
int
|
||||
_mesa_parse_instruction_suffix(const struct asm_parser_state *state,
|
||||
const char *suffix,
|
||||
struct prog_instruction *inst)
|
||||
{
|
||||
inst->CondUpdate = 0;
|
||||
inst->CondDst = 0;
|
||||
inst->SaturateMode = SATURATE_OFF;
|
||||
inst->Precision = FLOAT32;
|
||||
|
||||
|
||||
/* The first possible suffix element is the precision specifier from
|
||||
* NV_fragment_program_option.
|
||||
*/
|
||||
if (state->option.NV_fragment) {
|
||||
switch (suffix[0]) {
|
||||
case 'H':
|
||||
inst->Precision = FLOAT16;
|
||||
suffix++;
|
||||
break;
|
||||
case 'R':
|
||||
inst->Precision = FLOAT32;
|
||||
suffix++;
|
||||
break;
|
||||
case 'X':
|
||||
inst->Precision = FIXED12;
|
||||
suffix++;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* The next possible suffix element is the condition code modifier selection
|
||||
* from NV_fragment_program_option.
|
||||
*/
|
||||
if (state->option.NV_fragment) {
|
||||
if (suffix[0] == 'C') {
|
||||
inst->CondUpdate = 1;
|
||||
suffix++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* The final possible suffix element is the saturation selector from
|
||||
* ARB_fragment_program.
|
||||
*/
|
||||
if (state->mode == ARB_fragment) {
|
||||
if (strcmp(suffix, "_SAT") == 0) {
|
||||
inst->SaturateMode = SATURATE_ZERO_ONE;
|
||||
suffix += 4;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* It is an error for all of the suffix string not to be consumed.
|
||||
*/
|
||||
return suffix[0] == '\0';
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
_mesa_ARBvp_parse_option(struct asm_parser_state *state, const char *option)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -264,4 +264,18 @@ extern int _mesa_ARBvp_parse_option(struct asm_parser_state *state,
|
|||
extern int _mesa_ARBfp_parse_option(struct asm_parser_state *state,
|
||||
const char *option);
|
||||
|
||||
/**
|
||||
* Parses and processes instruction suffixes
|
||||
*
|
||||
* Instruction suffixes, such as \c _SAT, are processed. The relevant bits
|
||||
* are set in \c inst. If suffixes are encountered that are either not known
|
||||
* or not supported by the modes and options set in \c state, zero will be
|
||||
* returned.
|
||||
*
|
||||
* \return
|
||||
* Non-zero on success, zero on failure.
|
||||
*/
|
||||
extern int _mesa_parse_instruction_suffix(const struct asm_parser_state *state,
|
||||
const char *suffix, struct prog_instruction *inst);
|
||||
|
||||
/*@}*/
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue