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radeon/llvm: Remove auto-generated AMDIL->ISA conversion code
This commit is contained in:
Tom Stellard
parent
662ccbfc21
commit
d088da917b
14 changed files with 28 additions and 280 deletions
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@ -1,123 +0,0 @@
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#===-- AMDGPUGenInstrEnums.pl - Script for generating instruction enums ----===#
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#
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# The LLVM Compiler Infrastructure
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#
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# This file is distributed under the University of Illinois Open Source
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# License. See LICENSE.TXT for details.
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#
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#===-----------------------------------------------------------------------===#
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#
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# This perl script is used to generate the following files:
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#
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# 1. perl AMDGPUGenInstrEnums.pl td > AMDGPUInstrEnums.td
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#
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# This file contains Tablegen constants used for matching hw instructions
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# from R600 and SI with functionally similar AMDIL instruction. It aslo
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# contains definitions of floating point constants like pi (in hex notation)
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# that are used in some of the shader patterns.
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#
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# 2. perl AMDGPUGenInstrEnums.pl h > AMDGPUInstrEnums.h
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#
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# This file contains cpp enums that match the constant values in
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# AMDGPUInstrEnums.td
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#
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# 3. perl AMDGPUGenInstrEnums.pl inc > AMDGPUInstrEnums.include
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#
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# This file contains a function called GetRealAMDILOpcode which maps the
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# constant values defined in AMDGPUInstrEnums.h to the corresponding AMDIL
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# instructions.
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#===-----------------------------------------------------------------------===#
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use warnings;
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use strict;
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my @GENERATION_ENUM = qw {
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R600_CAYMAN
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R600
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EG
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EG_CAYMAN
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CAYMAN
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SI
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};
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my $FILE_TYPE = $ARGV[0];
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open AMDIL, '<', 'AMDILInstructions.td';
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my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'LOG_f32', 'RSQ_f32', 'SIN_f32', 'COS_f32');
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while (<AMDIL>) {
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if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+)</) {
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} elsif ($_ =~ /def\s+([A-Z_]+)(_[fi]32)/) {
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push @INST_ENUMS, "$1$2";
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}
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}
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if ($FILE_TYPE eq 'td') {
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print_td_enum('AMDILInst', 'AMDILInstEnums', 'field bits<16>', @INST_ENUMS);
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print_td_enum('AMDGPUGen', 'AMDGPUGenEnums', 'field bits<3>', @GENERATION_ENUM);
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my %constants = (
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'PI' => '0x40490fdb',
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'TWO_PI' => '0x40c90fdb',
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'TWO_PI_INV' => '0x3e22f983'
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);
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print "class Constants {\n";
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foreach (keys(%constants)) {
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print "int $_ = $constants{$_};\n";
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}
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print "}\n";
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print "def CONST : Constants;\n";
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} elsif ($FILE_TYPE eq 'h') {
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print "unsigned GetRealAMDILOpcode(unsigned internalOpcode) const;\n";
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print_h_enum('AMDILTblgenOpcode', @INST_ENUMS);
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print_h_enum('AMDGPUGen', @GENERATION_ENUM);
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} elsif ($FILE_TYPE eq 'inc') {
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print "unsigned AMDGPUInstrInfo::GetRealAMDILOpcode(unsigned internalOpcode) const\n{\n";
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print " switch(internalOpcode) {\n";
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#Start at 1 so we skip NONE
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for (my $i = 1; $i < scalar(@INST_ENUMS); $i++) {
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my $inst = $INST_ENUMS[$i];
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print " case AMDGPUInstrInfo::$inst: return AMDIL::$inst;\n";
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}
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print " default: abort();\n";
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print " }\n}\n";
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}
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sub print_td_enum {
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my ($instance, $class, $field, @values) = @_;
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print "class $class {\n";
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for (my $i = 0; $i < scalar(@values); $i++) {
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print " $field $values[$i] = $i;\n";
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}
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print "}\n";
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print "def $instance : $class;\n";
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}
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sub print_h_enum {
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my ($enum, @list) = @_;
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print "enum $enum {\n";
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for (my $i = 0; $i < scalar(@list); $i++) {
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print " $list[$i] = $i";
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if ($i != $#list) {
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print ',';
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}
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print "\n";
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}
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print "};\n";
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}
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@ -21,52 +21,7 @@
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using namespace llvm;
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AMDGPUInstrInfo::AMDGPUInstrInfo(AMDGPUTargetMachine &tm)
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: AMDILInstrInfo(tm), TM(tm)
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{
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const AMDILDevice * dev = TM.getSubtarget<AMDILSubtarget>().device();
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for (unsigned i = 0; i < AMDIL::INSTRUCTION_LIST_END; i++) {
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const MCInstrDesc & instDesc = get(i);
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uint32_t instGen = (instDesc.TSFlags >> 40) & 0x7;
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uint32_t inst = (instDesc.TSFlags >> 48) & 0xffff;
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if (inst == 0) {
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continue;
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}
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switch (instGen) {
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case AMDGPUInstrInfo::R600_CAYMAN:
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if (dev->getGeneration() > AMDILDeviceInfo::HD6XXX) {
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continue;
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}
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break;
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case AMDGPUInstrInfo::R600:
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if (dev->getGeneration() != AMDILDeviceInfo::HD4XXX) {
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continue;
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}
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break;
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case AMDGPUInstrInfo::EG_CAYMAN:
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if (dev->getGeneration() < AMDILDeviceInfo::HD5XXX
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|| dev->getGeneration() > AMDILDeviceInfo::HD6XXX) {
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continue;
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}
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break;
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case AMDGPUInstrInfo::CAYMAN:
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if (dev->getDeviceFlag() != OCL_DEVICE_CAYMAN) {
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continue;
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}
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break;
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case AMDGPUInstrInfo::SI:
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if (dev->getGeneration() != AMDILDeviceInfo::HD7XXX) {
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continue;
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}
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break;
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default:
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abort();
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break;
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}
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unsigned amdilOpcode = GetRealAMDILOpcode(inst);
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amdilToISA[amdilOpcode] = instDesc.Opcode;
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}
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}
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: AMDILInstrInfo(tm), TM(tm) { }
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MachineInstr * AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF,
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DebugLoc DL) const
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@ -98,14 +53,3 @@ MachineInstr * AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction
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return newInstr;
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}
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unsigned AMDGPUInstrInfo::getISAOpcode(unsigned opcode) const
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{
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if (amdilToISA.count(opcode) == 0) {
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return opcode;
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} else {
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return amdilToISA.find(opcode)->second;
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}
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}
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#include "AMDGPUInstrEnums.include"
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@ -30,7 +30,6 @@ class MachineInstrBuilder;
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class AMDGPUInstrInfo : public AMDILInstrInfo {
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private:
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AMDGPUTargetMachine & TM;
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std::map<unsigned, unsigned> amdilToISA;
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public:
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explicit AMDGPUInstrInfo(AMDGPUTargetMachine &tm);
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@ -39,14 +38,13 @@ public:
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/// getISAOpcode - This function takes an AMDIL opcode as an argument and
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/// returns an equivalent ISA opcode.
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virtual unsigned getISAOpcode(unsigned AMDILopcode) const;
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virtual unsigned getISAOpcode(unsigned AMDILopcode) const = 0;
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/// convertToISA - Convert the AMDIL MachineInstr to a supported ISA
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/// MachineInstr
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virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF,
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DebugLoc DL) const;
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#include "AMDGPUInstrEnums.h.include"
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};
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} // End llvm namespace
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@ -12,8 +12,6 @@
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//
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//===----------------------------------------------------------------------===//
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include "AMDGPUInstrEnums.td"
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class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
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field bits<16> AMDILOp = 0;
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field bits<3> Gen = 0;
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@ -34,6 +32,13 @@ class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
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}
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class Constants {
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int TWO_PI = 0x40c90fdb;
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int PI = 0x40490fdb;
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int TWO_PI_INV = 0x3e22f983;
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}
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def CONST : Constants;
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let isCodeGenOnly = 1 in {
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def MASK_WRITE : AMDGPUShaderInst <
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@ -44,21 +44,18 @@ bool AMDGPU::isTransOp(unsigned opcode)
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switch(opcode) {
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default: return false;
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case AMDIL::COS_f32:
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case AMDIL::COS_r600:
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case AMDIL::COS_eg:
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case AMDIL::RSQ_f32:
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case AMDIL::MULLIT:
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case AMDIL::MUL_LIT_r600:
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case AMDIL::MUL_LIT_eg:
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case AMDIL::SIN_f32:
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case AMDIL::EXP_IEEE_r600:
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case AMDIL::EXP_IEEE_eg:
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case AMDIL::LOG_CLAMPED_r600:
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case AMDIL::LOG_IEEE_r600:
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case AMDIL::LOG_CLAMPED_eg:
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case AMDIL::LOG_IEEE_eg:
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case AMDIL::LOG_f32:
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return true;
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}
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}
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@ -206,8 +206,6 @@ defm ACOS : UnaryIntrinsicFloatScalar<IL_OP_ACOS, int_AMDIL_acos>;
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defm ATAN : UnaryIntrinsicFloatScalar<IL_OP_ATAN, int_AMDIL_atan>;
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defm ASIN : UnaryIntrinsicFloatScalar<IL_OP_ASIN, int_AMDIL_asin>;
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defm TAN : UnaryIntrinsicFloatScalar<IL_OP_TAN, int_AMDIL_tan>;
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defm SIN : UnaryIntrinsicFloatScalar<IL_OP_SIN, int_AMDIL_sin>;
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defm COS : UnaryIntrinsicFloatScalar<IL_OP_COS, int_AMDIL_cos>;
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defm SQRT : UnaryIntrinsicFloatScalar<IL_OP_SQRT, int_AMDIL_sqrt>;
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defm SQRTVEC : UnaryIntrinsicFloat<IL_OP_SQRT_VEC, int_AMDIL_sqrt_vec>;
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defm COSVEC : UnaryIntrinsicFloat<IL_OP_COS_VEC, int_AMDIL_cos_vec>;
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@ -228,7 +226,6 @@ defm MOD : BinaryOpMCf32<IL_OP_MOD, frem>;
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let hasZeroOpFlag = 1 in {
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let mayLoad = 0, mayStore=0 in {
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defm LN : UnaryIntrinsicFloatScalar<IL_OP_LN, int_AMDIL_ln>;
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defm LOG : UnaryIntrinsicFloatScalar<IL_OP_LOG, int_AMDIL_log>;
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defm RSQ : UnaryIntrinsicFloatScalar<IL_OP_RSQ, int_AMDIL_rsq>;
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defm DIV : BinaryIntrinsicFloat<IL_OP_DIV, int_AMDIL_div>;
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}
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@ -38,16 +38,6 @@ endif
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R600RegisterInfo.td: R600GenRegisterInfo.pl
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$(PERL) $^ > $@
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AMDGPUInstrEnums.td: AMDGPUGenInstrEnums.pl
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$(PERL) $^ td > $@
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AMDGPUInstrEnums.h.include: AMDGPUGenInstrEnums.pl
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$(PERL) $^ h > $@
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AMDGPUInstrEnums.include: AMDGPUGenInstrEnums.pl
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$(PERL) $^ inc > $@
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AMDILGenRegisterInfo.inc: *.td
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$(call tablegen, -gen-register-info, AMDIL.td, $@)
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@ -2,7 +2,6 @@
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GENERATED_SOURCES := \
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R600Intrinsics.td \
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R600RegisterInfo.td \
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AMDGPUInstrEnums.td \
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SIRegisterInfo.td \
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SIRegisterGetHWRegNum.inc \
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AMDILGenRegisterInfo.inc \
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@ -13,9 +12,7 @@ GENERATED_SOURCES := \
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AMDILGenSubtargetInfo.inc \
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AMDILGenEDInfo.inc \
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AMDILGenIntrinsics.inc \
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AMDILGenCodeEmitter.inc \
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AMDGPUInstrEnums.h.include \
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AMDGPUInstrEnums.include
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AMDILGenCodeEmitter.inc
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CPP_SOURCES := \
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AMDIL7XXDevice.cpp \
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@ -64,7 +64,7 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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unsigned R600InstrInfo::getISAOpcode(unsigned opcode) const
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{
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switch (opcode) {
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default: return AMDGPUInstrInfo::getISAOpcode(opcode);
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default: return opcode;
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case AMDIL::IEQ:
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return AMDIL::SETE_INT;
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case AMDIL::INE:
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@ -22,13 +22,6 @@
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namespace llvm {
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struct InstrGroup {
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unsigned amdil;
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unsigned r600;
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unsigned eg;
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unsigned cayman;
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};
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class AMDGPUTargetMachine;
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class MachineFunction;
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class MachineInstr;
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@ -291,8 +291,6 @@ let Predicates = [isR600toCayman] in {
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/* ------------------------------------------- */
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/* Common Instructions R600, R700, Evergreen, Cayman */
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/* ------------------------------------------- */
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let Gen = AMDGPUGen.R600_CAYMAN in {
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def ADD : R600_2OP <
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0x0, "ADD",
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[(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
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@ -330,7 +328,6 @@ def SETE : R600_2OP <
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(selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
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COND_EQ))]
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>;
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//let AMDILOp = AMDILInst.FEQ;
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def SGT : R600_2OP <
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0x09, "SETGT",
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@ -345,7 +342,6 @@ def SGE : R600_2OP <
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(selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
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COND_GE))]
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>;
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//let AMDILOp = AMDILInst.FGE;
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def SNE : R600_2OP <
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0xB, "SETNE",
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@ -354,8 +350,6 @@ def SNE : R600_2OP <
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COND_NE))]
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>;
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// let AMDILOp = AMDILInst.FNE;
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def FRACT : R600_1OP <
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0x10, "FRACT",
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[(set R600_Reg32:$dst, (AMDGPUfract R600_Reg32:$src))]
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@ -442,8 +436,6 @@ def SETE_INT : R600_2OP <
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(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
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>;
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// let AMDILOp = AMDILInst.IEQ;
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def SETGT_INT : R600_2OP <
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0x3B, "SGT_INT",
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[(set (i32 R600_Reg32:$dst),
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@ -455,16 +447,12 @@ def SETGE_INT : R600_2OP <
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[(set (i32 R600_Reg32:$dst),
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(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
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>;
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// let AMDILOp = AMDILInst.IGE;
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def SETNE_INT : R600_2OP <
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0x3D, "SETNE_INT",
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[(set (i32 R600_Reg32:$dst),
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(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
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>;
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//let AMDILOp = AMDILInst.INE;
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def SETGT_UINT : R600_2OP <
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0x3E, "SETGT_UINT",
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@ -472,14 +460,11 @@ def SETGT_UINT : R600_2OP <
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(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
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>;
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// let AMDILOp = AMDILInst.UGT;
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def SETGE_UINT : R600_2OP <
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0x3F, "SETGE_UINT",
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[(set (i32 R600_Reg32:$dst),
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(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
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>;
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// let AMDILOp = AMDILInst.UGE;
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def CNDE_INT : R600_3OP <
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0x1C, "CNDE_INT",
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@ -563,8 +548,6 @@ def TEX_SAMPLE_C_G : R600_TEX <
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[]
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>;
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} // End Gen R600_CAYMAN
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def KILP : Pat <
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(int_AMDGPU_kilp),
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(MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
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@ -642,9 +625,8 @@ class LOG_CLAMPED_Common <bits<32> inst> : R600_1OP <
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class LOG_IEEE_Common <bits<32> inst> : R600_1OP <
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inst, "LOG_IEEE",
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[]> {
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let AMDILOp = AMDILInst.LOG_f32;
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}
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[(set R600_Reg32:$dst, (int_AMDIL_log R600_Reg32:$src))]
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>;
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class LSHL_Common <bits<32> inst> : R600_2OP <
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inst, "LSHL $dst, $src0, $src1",
|
||||
|
|
@ -688,9 +670,8 @@ class RECIP_CLAMPED_Common <bits<32> inst> : R600_1OP <
|
|||
|
||||
class RECIP_IEEE_Common <bits<32> inst> : R600_1OP <
|
||||
inst, "RECIP_IEEE",
|
||||
[(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]> {
|
||||
let AMDILOp = AMDILInst.RSQ_f32;
|
||||
}
|
||||
[(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]
|
||||
>;
|
||||
|
||||
class RECIP_UINT_Common <bits<32> inst> : R600_1OP <
|
||||
inst, "RECIP_INT $dst, $src",
|
||||
|
|
@ -709,15 +690,13 @@ class RECIPSQRT_IEEE_Common <bits<32> inst> : R600_1OP <
|
|||
|
||||
class SIN_Common <bits<32> inst> : R600_1OP <
|
||||
inst, "SIN",
|
||||
[]>{
|
||||
let AMDILOp = AMDILInst.SIN_f32;
|
||||
[(set R600_Reg32:$dst, (int_AMDIL_sin R600_Reg32:$src))]>{
|
||||
let Trig = 1;
|
||||
}
|
||||
|
||||
class COS_Common <bits<32> inst> : R600_1OP <
|
||||
inst, "COS",
|
||||
[]> {
|
||||
let AMDILOp = AMDILInst.COS_f32;
|
||||
[(set R600_Reg32:$dst, (int_AMDIL_cos R600_Reg32:$src))]> {
|
||||
let Trig = 1;
|
||||
}
|
||||
|
||||
|
|
@ -745,8 +724,6 @@ class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ie
|
|||
|
||||
let Predicates = [isR600] in {
|
||||
|
||||
let Gen = AMDGPUGen.R600 in {
|
||||
|
||||
def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
|
||||
def MULADD_r600 : MULADD_Common<0x10>;
|
||||
def CNDE_r600 : CNDE_Common<0x18>;
|
||||
|
|
@ -774,8 +751,6 @@ let Gen = AMDGPUGen.R600 in {
|
|||
def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
|
||||
def RECIP_UINT_r600 : RECIP_UINT_Common <0x77>;
|
||||
|
||||
} // End AMDGPUGen.R600
|
||||
|
||||
def DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
|
||||
def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
|
||||
def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>;
|
||||
|
|
@ -801,8 +776,6 @@ class TRIG_HELPER_r700 <InstR600 trig_inst>: Pat <
|
|||
|
||||
let Predicates = [isEG] in {
|
||||
|
||||
let Gen = AMDGPUGen.EG in {
|
||||
|
||||
def RAT_WRITE_CACHELESS_eg :
|
||||
EG_CF_RAT <0x57, 0x2, (outs), (ins R600_TReg32_X:$rw_gpr,
|
||||
R600_TReg32_X:$index_gpr, i32imm:$rat_id), "">
|
||||
|
|
@ -891,9 +864,6 @@ def VTX_READ_eg : InstR600ISA < (outs R600_TReg32_X:$dst),
|
|||
*/
|
||||
}
|
||||
|
||||
|
||||
|
||||
} // End AMDGPUGen.EG
|
||||
/* XXX: Need to convert PTR to rat_id */
|
||||
/*
|
||||
def : Pat <(store_global (f32 R600_Reg32:$value), node:$ptr),
|
||||
|
|
@ -923,8 +893,6 @@ class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
|
|||
(trig (MUL (MOV (LOADCONST_i32 CONST.TWO_PI_INV)), R600_Reg32:$src))
|
||||
>;
|
||||
|
||||
let Gen = AMDGPUGen.EG_CAYMAN in {
|
||||
|
||||
def MULADD_eg : MULADD_Common<0x14>;
|
||||
def ASHR_eg : ASHR_Common<0x15>;
|
||||
def LSHR_eg : LSHR_Common<0x16>;
|
||||
|
|
@ -952,8 +920,6 @@ let Gen = AMDGPUGen.EG_CAYMAN in {
|
|||
def DOT4_eg : DOT4_Common<0xBE>;
|
||||
def CUBE_eg : CUBE_Common<0xC0>;
|
||||
|
||||
} // End AMDGPUGen.EG_CAYMAN
|
||||
|
||||
def DIV_eg : DIV_Common<RECIP_IEEE_eg>;
|
||||
def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>;
|
||||
def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
|
||||
|
|
@ -966,13 +932,9 @@ let Gen = AMDGPUGen.EG_CAYMAN in {
|
|||
|
||||
let Predicates = [isCayman] in {
|
||||
|
||||
let Gen = AMDGPUGen.CAYMAN in {
|
||||
|
||||
/* XXX: I'm not sure if this opcode is correct. */
|
||||
def RECIP_UINT_cm : RECIP_UINT_Common<0x77>;
|
||||
|
||||
} // End AMDGPUGen.CAYMAN
|
||||
|
||||
} // End isCayman
|
||||
|
||||
/* Other Instructions */
|
||||
|
|
|
|||
|
|
@ -47,16 +47,10 @@ class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
|
|||
op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
|
||||
>;
|
||||
|
||||
multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern,
|
||||
bits<16> amdil = AMDILInst.NONE> {
|
||||
|
||||
let AMDILOp = amdil in {
|
||||
def _e32: VOP1_Helper <op, VReg_32, AllReg_32, opName, pattern>;
|
||||
}
|
||||
|
||||
def _e64 : VOP3_32 <
|
||||
{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
|
||||
opName, []
|
||||
multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> {
|
||||
def _e32: VOP1_Helper <op, VReg_32, AllReg_32, opName, pattern>;
|
||||
def _e64 : VOP3_32 <{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
|
||||
opName, []
|
||||
>;
|
||||
}
|
||||
|
||||
|
|
@ -76,16 +70,12 @@ class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
|
|||
op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
|
||||
>;
|
||||
|
||||
multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern,
|
||||
bits<16> amdil = AMDILInst.NONE> {
|
||||
multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> {
|
||||
|
||||
let AMDILOp = amdil in {
|
||||
def _e32 : VOP2_Helper <op, VReg_32, AllReg_32, opName, pattern>;
|
||||
}
|
||||
def _e32 : VOP2_Helper <op, VReg_32, AllReg_32, opName, pattern>;
|
||||
|
||||
def _e64 : VOP3_32 <
|
||||
{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
|
||||
opName, []
|
||||
def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
|
||||
opName, []
|
||||
>;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -108,7 +108,8 @@ unsigned SIInstrInfo::getISAOpcode(unsigned AMDILopcode) const
|
|||
switch (AMDILopcode) {
|
||||
//XXX We need a better way of detecting end of program
|
||||
case AMDIL::RETURN: return AMDIL::S_ENDPGM;
|
||||
default: return AMDGPUInstrInfo::getISAOpcode(AMDILopcode);
|
||||
case AMDIL::MOVE_f32: return AMDIL::V_MOV_B32_e32;
|
||||
default: return AMDILopcode;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@ def isSI : Predicate<"Subtarget.device()"
|
|||
"->getGeneration() == AMDILDeviceInfo::HD7XXX">;
|
||||
|
||||
let Predicates = [isSI] in {
|
||||
let Gen = AMDGPUGen.SI in {
|
||||
|
||||
def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
|
||||
def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
|
||||
|
|
@ -462,7 +461,7 @@ def IMAGE_SAMPLE : MIMG_Load_Helper <0x00000020, "IMAGE_SAMPLE">;
|
|||
//def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
|
||||
|
||||
let neverHasSideEffects = 1 in {
|
||||
defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", [], AMDILInst.MOVE_f32>;
|
||||
defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>;
|
||||
} // End neverHasSideEffects
|
||||
defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>;
|
||||
//defm V_CVT_I32_F64 : VOP1_32 <0x00000003, "V_CVT_I32_F64", []>;
|
||||
|
|
@ -865,8 +864,6 @@ def VS_LOAD_BUFFER_INDEX : InstSI <
|
|||
|
||||
} // end IsCodeGenOnly, isPseudo
|
||||
|
||||
} // end Gen = AMDGPUGen.SI
|
||||
|
||||
/* int_SI_vs_load_input */
|
||||
def : Pat<
|
||||
(int_SI_vs_load_input SReg_64:$tlst_sgpr, IMM8bit:$t_offset, IMM12bit:$attr_offset,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue