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i965/vec4: Plumb separate surfaces and samplers through from NIR

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Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jason Ekstrand 2015-11-02 18:39:17 -08:00
parent f88027f7bd
commit d03e5d5255
4 changed files with 23 additions and 9 deletions
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3
src/mesa/drivers/dri/i965/brw_vec4.h
View file

@ -260,10 +260,11 @@ public:
src_reg offset_value,
src_reg mcs,
bool is_cube_array,
uint32_t surface, src_reg surface_reg,
uint32_t sampler, src_reg sampler_reg);
src_reg emit_mcs_fetch(const glsl_type *coordinate_type, src_reg coordinate,
src_reg sampler);
src_reg surface);
void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
void emit_ndc_computation();

2
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
View file

@ -1675,7 +1675,7 @@ generate_code(struct brw_codegen *p,
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_SAMPLEINFO:
generate_tex(p, prog_data, inst, dst, src[0], src[1], src[1]);
generate_tex(p, prog_data, inst, dst, src[0], src[1], src[2]);
break;
case VS_OPCODE_URB_WRITE:

15
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
View file

@ -1640,7 +1640,9 @@ void
vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
{
unsigned texture = instr->texture_index;
unsigned sampler = instr->sampler_index;
src_reg texture_reg = brw_imm_ud(texture);
src_reg sampler_reg = brw_imm_ud(sampler);
src_reg coordinate;
const glsl_type *coord_type = NULL;
src_reg shadow_comparitor;
@ -1738,8 +1740,14 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
break;
}
case nir_tex_src_sampler_offset:
break; /* Ignored for now */
case nir_tex_src_sampler_offset: {
/* Emit code to evaluate the actual indexing expression */
src_reg src = get_nir_src(instr->src[i].src, 1);
src_reg temp(this, glsl_type::uint_type);
emit(ADD(dst_reg(temp), src, brw_imm_ud(sampler)));
sampler_reg = emit_uniformize(temp);
break;
}
case nir_tex_src_projector:
unreachable("Should be lowered by do_lower_texture_projection");
@ -1795,7 +1803,8 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
shadow_comparitor,
lod, lod2, sample_index,
constant_offset, offset_value,
mcs, is_cube_array, texture, texture_reg);
mcs, is_cube_array,
texture, texture_reg, sampler, sampler_reg);
}
void

12
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
View file

@ -815,13 +815,14 @@ vec4_visitor::emit_uniformize(const src_reg &src)
src_reg
vec4_visitor::emit_mcs_fetch(const glsl_type *coordinate_type,
src_reg coordinate, src_reg sampler)
src_reg coordinate, src_reg surface)
{
vec4_instruction *inst =
new(mem_ctx) vec4_instruction(SHADER_OPCODE_TXF_MCS,
dst_reg(this, glsl_type::uvec4_type));
inst->base_mrf = 2;
inst->src[1] = sampler;
inst->src[1] = surface;
inst->src[2] = surface;
int param_base;
@ -877,6 +878,8 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
src_reg offset_value,
src_reg mcs,
bool is_cube_array,
uint32_t surface,
src_reg surface_reg,
uint32_t sampler,
src_reg sampler_reg)
{
@ -942,7 +945,8 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
inst->dst.writemask = WRITEMASK_XYZW;
inst->shadow_compare = shadow_comparitor.file != BAD_FILE;
inst->src[1] = sampler_reg;
inst->src[1] = surface_reg;
inst->src[2] = sampler_reg;
/* MRF for the first parameter */
int param_base = inst->base_mrf + inst->header_size;
@ -1068,7 +1072,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
}
if (devinfo->gen == 6 && op == ir_tg4) {
emit_gen6_gather_wa(key_tex->gen6_gather_wa[sampler], inst->dst);
emit_gen6_gather_wa(key_tex->gen6_gather_wa[surface], inst->dst);
}
if (op == ir_query_levels) {