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pan/va: Use invalid_instruction in more places
By passing the instruction pointer through the packer, we can get better error messages with invalid_instruction. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17224>
This commit is contained in:
Alyssa Rosenzweig
Marge Bot
parent
cc94409d70
commit
cfeafef755
1 changed files with 73 additions and 65 deletions
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@ -35,12 +35,20 @@
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* Unreachable for encoding failures, when hitting an invalid instruction.
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* Prints the (first) failing instruction to aid debugging.
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*/
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NORETURN static void
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invalid_instruction(const bi_instr *I, const char *cause)
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NORETURN static void PRINTFLIKE(2, 3)
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invalid_instruction(const bi_instr *I, const char *cause, ...)
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{
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fprintf(stderr, "\nPacking failure due to invalid %s:\n\t", cause);
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fputs("\nInvalid ", stderr);
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va_list ap;
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va_start(ap, cause);
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vfprintf(stderr, cause, ap);
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va_end(ap);
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fputs(":\n\t", stderr);
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bi_print_instr(I, stderr);
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fprintf(stderr, "\n");
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unreachable("Invalid instruction");
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}
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@ -76,7 +84,7 @@ va_pack_reg(bi_index idx)
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}
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static unsigned
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va_pack_fau_special(enum bir_fau fau)
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va_pack_fau_special(const bi_instr *I, enum bir_fau fau)
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{
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switch (fau) {
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case BIR_FAU_ATEST_PARAM: return VA_FAU_SPECIAL_PAGE_0_ATEST_DATUM;
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@ -90,7 +98,7 @@ va_pack_fau_special(enum bir_fau fau)
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return VA_FAU_SPECIAL_PAGE_0_BLEND_DESCRIPTOR_0 + (fau - BIR_FAU_BLEND_0);
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default:
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unreachable("Unknown FAU value");
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invalid_instruction(I, "FAU");
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}
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}
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@ -99,7 +107,7 @@ va_pack_fau_special(enum bir_fau fau)
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* used to encode a 32-bit FAU source by or'ing in the appropriate offset.
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*/
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static unsigned
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va_pack_fau_64(bi_index idx)
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va_pack_fau_64(const bi_instr *I, bi_index idx)
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{
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assert(idx.type == BI_INDEX_FAU);
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@ -110,39 +118,41 @@ va_pack_fau_64(bi_index idx)
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else if (idx.value & BIR_FAU_UNIFORM)
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return (0x2 << 6) | (val << 1);
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else
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return (0x7 << 5) | (va_pack_fau_special(idx.value) << 1);
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return (0x7 << 5) | (va_pack_fau_special(I, idx.value) << 1);
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}
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static unsigned
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va_pack_src(bi_index idx)
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va_pack_src(const bi_instr *I, unsigned s)
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{
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bi_index idx = I->src[s];
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if (idx.type == BI_INDEX_REGISTER) {
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unsigned value = va_pack_reg(idx);
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if (idx.discard) value |= (1 << 6);
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return value;
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} else if (idx.type == BI_INDEX_FAU) {
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assert(idx.offset <= 1);
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return va_pack_fau_64(idx) | idx.offset;
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return va_pack_fau_64(I, idx) | idx.offset;
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}
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unreachable("Invalid type");
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invalid_instruction(I, "type of source %u", s);
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}
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static unsigned
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va_pack_wrmask(enum bi_swizzle swz)
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va_pack_wrmask(const bi_instr *I)
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{
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switch (swz) {
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switch (I->dest[0].swizzle) {
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case BI_SWIZZLE_H00: return 0x1;
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case BI_SWIZZLE_H11: return 0x2;
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case BI_SWIZZLE_H01: return 0x3;
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default: unreachable("Invalid write mask");
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default: invalid_instruction(I, "write mask");
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}
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}
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static enum va_atomic_operation
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va_pack_atom_opc(enum bi_atom_opc opc)
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va_pack_atom_opc(const bi_instr *I)
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{
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switch (opc) {
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switch (I->atom_opc) {
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case BI_ATOM_OPC_AADD: return VA_ATOMIC_OPERATION_AADD;
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case BI_ATOM_OPC_ASMIN: return VA_ATOMIC_OPERATION_ASMIN;
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case BI_ATOM_OPC_ASMAX: return VA_ATOMIC_OPERATION_ASMAX;
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@ -153,54 +163,54 @@ va_pack_atom_opc(enum bi_atom_opc opc)
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case BI_ATOM_OPC_AXOR: return VA_ATOMIC_OPERATION_AXOR;
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case BI_ATOM_OPC_ACMPXCHG:
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case BI_ATOM_OPC_AXCHG: return VA_ATOMIC_OPERATION_AXCHG;
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default: unreachable("Invalid atom_opc");
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default: invalid_instruction(I, "atomic opcode");
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}
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}
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static enum va_atomic_operation_with_1
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va_pack_atom_opc_1(enum bi_atom_opc opc)
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va_pack_atom_opc_1(const bi_instr *I)
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{
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switch (opc) {
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switch (I->atom_opc) {
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case BI_ATOM_OPC_AINC: return VA_ATOMIC_OPERATION_WITH_1_AINC;
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case BI_ATOM_OPC_ADEC: return VA_ATOMIC_OPERATION_WITH_1_ADEC;
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case BI_ATOM_OPC_AUMAX1: return VA_ATOMIC_OPERATION_WITH_1_AUMAX1;
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case BI_ATOM_OPC_ASMAX1: return VA_ATOMIC_OPERATION_WITH_1_ASMAX1;
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case BI_ATOM_OPC_AOR1: return VA_ATOMIC_OPERATION_WITH_1_AOR1;
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default: unreachable("Invalid atom_opc");
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default: invalid_instruction(I, "atomic opcode with implicit 1");
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}
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}
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static unsigned
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va_pack_dest(bi_index index)
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va_pack_dest(const bi_instr *I)
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{
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return va_pack_reg(index) | (va_pack_wrmask(index.swizzle) << 6);
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return va_pack_reg(I->dest[0]) | (va_pack_wrmask(I) << 6);
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}
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static enum va_widen
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va_pack_widen_f32(enum bi_swizzle swz)
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va_pack_widen_f32(const bi_instr *I, enum bi_swizzle swz)
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{
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switch (swz) {
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case BI_SWIZZLE_H01: return VA_WIDEN_NONE;
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case BI_SWIZZLE_H00: return VA_WIDEN_H0;
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case BI_SWIZZLE_H11: return VA_WIDEN_H1;
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default: unreachable("Invalid widen");
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default: invalid_instruction(I, "widen");
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}
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}
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static enum va_swizzles_16_bit
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va_pack_swizzle_f16(enum bi_swizzle swz)
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va_pack_swizzle_f16(const bi_instr *I, enum bi_swizzle swz)
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{
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switch (swz) {
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case BI_SWIZZLE_H00: return VA_SWIZZLES_16_BIT_H00;
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case BI_SWIZZLE_H10: return VA_SWIZZLES_16_BIT_H10;
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case BI_SWIZZLE_H01: return VA_SWIZZLES_16_BIT_H01;
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case BI_SWIZZLE_H11: return VA_SWIZZLES_16_BIT_H11;
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default: unreachable("Invalid swizzle");
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default: invalid_instruction(I, "16-bit swizzle");
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}
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}
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static unsigned
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va_pack_widen(enum bi_swizzle swz, enum va_size size)
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va_pack_widen(const bi_instr *I, enum bi_swizzle swz, enum va_size size)
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{
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if (size == VA_SIZE_8) {
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switch (swz) {
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@ -211,7 +221,7 @@ va_pack_widen(enum bi_swizzle swz, enum va_size size)
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case BI_SWIZZLE_B1111: return VA_SWIZZLES_8_BIT_B1111;
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case BI_SWIZZLE_B2222: return VA_SWIZZLES_8_BIT_B2222;
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case BI_SWIZZLE_B3333: return VA_SWIZZLES_8_BIT_B3333;
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default: unreachable("Exotic swizzles not yet handled");
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default: invalid_instruction(I, "8-bit widen");
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}
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} else if (size == VA_SIZE_16) {
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switch (swz) {
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@ -223,7 +233,7 @@ va_pack_widen(enum bi_swizzle swz, enum va_size size)
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case BI_SWIZZLE_B1111: return VA_SWIZZLES_16_BIT_B11;
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case BI_SWIZZLE_B2222: return VA_SWIZZLES_16_BIT_B22;
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case BI_SWIZZLE_B3333: return VA_SWIZZLES_16_BIT_B33;
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default: unreachable("Exotic swizzles not yet handled");
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default: invalid_instruction(I, "16-bit widen");
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}
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} else if (size == VA_SIZE_32) {
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switch (swz) {
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@ -234,15 +244,15 @@ va_pack_widen(enum bi_swizzle swz, enum va_size size)
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case BI_SWIZZLE_B1111: return VA_SWIZZLES_32_BIT_B1;
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case BI_SWIZZLE_B2222: return VA_SWIZZLES_32_BIT_B2;
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case BI_SWIZZLE_B3333: return VA_SWIZZLES_32_BIT_B3;
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default: unreachable("Invalid swizzle");
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default: invalid_instruction(I, "32-bit widen");
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}
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} else {
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unreachable("TODO: other type sizes");
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invalid_instruction(I, "type size for widen");
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}
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}
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static enum va_half_swizzles_8_bit
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va_pack_halfswizzle(enum bi_swizzle swz)
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va_pack_halfswizzle(const bi_instr *I, enum bi_swizzle swz)
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{
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switch (swz) {
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case BI_SWIZZLE_B0000: return VA_HALF_SWIZZLES_8_BIT_B00;
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@ -252,12 +262,12 @@ va_pack_halfswizzle(enum bi_swizzle swz)
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case BI_SWIZZLE_B0011: return VA_HALF_SWIZZLES_8_BIT_B01;
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case BI_SWIZZLE_B2233: return VA_HALF_SWIZZLES_8_BIT_B23;
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case BI_SWIZZLE_B0022: return VA_HALF_SWIZZLES_8_BIT_B02;
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default: unreachable("todo: more halfswizzles");
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default: invalid_instruction(I, "v2u8 swizzle");
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}
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}
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static enum va_lanes_8_bit
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va_pack_shift_lanes(enum bi_swizzle swz)
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va_pack_shift_lanes(const bi_instr *I, enum bi_swizzle swz)
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{
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switch (swz) {
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case BI_SWIZZLE_H01: return VA_LANES_8_BIT_B02;
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@ -265,18 +275,18 @@ va_pack_shift_lanes(enum bi_swizzle swz)
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case BI_SWIZZLE_B1111: return VA_LANES_8_BIT_B11;
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case BI_SWIZZLE_B2222: return VA_LANES_8_BIT_B22;
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case BI_SWIZZLE_B3333: return VA_LANES_8_BIT_B33;
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default: unreachable("todo: more shifts");
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default: invalid_instruction(I, "lane shift");
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}
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}
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static enum va_combine
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va_pack_combine(enum bi_swizzle swz)
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va_pack_combine(const bi_instr *I, enum bi_swizzle swz)
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{
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switch (swz) {
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case BI_SWIZZLE_H01: return VA_COMBINE_NONE;
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case BI_SWIZZLE_H00: return VA_COMBINE_H0;
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case BI_SWIZZLE_H11: return VA_COMBINE_H1;
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default: unreachable("Invalid branch lane");
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default: invalid_instruction(I, "branch lane");
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}
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}
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@ -422,7 +432,7 @@ va_pack_alu(const bi_instr *I)
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* added elsewhere, as they require special handling for control fields.
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*/
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if (info.has_dest && info.nr_staging_dests == 0) {
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hex |= (uint64_t) va_pack_dest(I->dest[0]) << 40;
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hex |= (uint64_t) va_pack_dest(I) << 40;
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} else if (info.nr_staging_dests == 0 && info.nr_staging_srcs == 0) {
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assert(bi_is_null(I->dest[0]));
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hex |= 0xC0ull << 40; /* Placeholder */
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@ -440,7 +450,7 @@ va_pack_alu(const bi_instr *I)
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enum va_size size = src_info.size;
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bi_index src = I->src[logical_i + src_offset];
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hex |= (uint64_t) va_pack_src(src) << (8 * i);
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hex |= (uint64_t) va_pack_src(I, logical_i + src_offset) << (8 * i);
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if (src_info.notted) {
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if (src.neg) hex |= (1ull << 35);
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@ -460,11 +470,11 @@ va_pack_alu(const bi_instr *I)
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unsigned S = src.swizzle;
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assert(size == VA_SIZE_16 || size == VA_SIZE_32);
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uint64_t v = (size == VA_SIZE_32 ? va_pack_widen_f32(S) : va_pack_swizzle_f16(S));
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uint64_t v = (size == VA_SIZE_32 ? va_pack_widen_f32(I, S) : va_pack_swizzle_f16(I, S));
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hex |= v << offs;
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} else if (src_info.widen) {
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unsigned offs = (i == 1) ? 26 : 36;
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hex |= (uint64_t) va_pack_widen(src.swizzle, src_info.size) << offs;
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hex |= (uint64_t) va_pack_widen(I, src.swizzle, src_info.size) << offs;
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} else if (src_info.lane) {
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unsigned offs = (I->op == BI_OPCODE_MKVEC_V2I8) ?
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((i == 0) ? 38 : 36) :
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@ -473,7 +483,7 @@ va_pack_alu(const bi_instr *I)
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if (src_info.size == VA_SIZE_16) {
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hex |= (src.swizzle == BI_SWIZZLE_H11 ? 1 : 0) << offs;
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} else if (I->op == BI_OPCODE_BRANCHZ_I16) {
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hex |= ((uint64_t) va_pack_combine(src.swizzle) << 37);
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hex |= ((uint64_t) va_pack_combine(I, src.swizzle) << 37);
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} else {
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assert(src_info.size == VA_SIZE_8);
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unsigned comp = src.swizzle - BI_SWIZZLE_B0000;
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@ -483,16 +493,16 @@ va_pack_alu(const bi_instr *I)
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} else if (src_info.lanes) {
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assert(src_info.size == VA_SIZE_8);
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assert(i == 1);
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hex |= (uint64_t) va_pack_shift_lanes(src.swizzle) << 26;
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hex |= (uint64_t) va_pack_shift_lanes(I, src.swizzle) << 26;
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} else if (src_info.combine) {
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/* Treat as swizzle, subgroup ops not yet supported */
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assert(src_info.size == VA_SIZE_32);
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assert(i == 0);
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hex |= (uint64_t) va_pack_widen_f32(src.swizzle) << 37;
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hex |= (uint64_t) va_pack_widen_f32(I, src.swizzle) << 37;
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} else if (src_info.halfswizzle) {
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assert(src_info.size == VA_SIZE_8);
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assert(i == 0);
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hex |= (uint64_t) va_pack_halfswizzle(src.swizzle) << 36;
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hex |= (uint64_t) va_pack_halfswizzle(I, src.swizzle) << 36;
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} else if (src.swizzle != BI_SWIZZLE_H01) {
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invalid_instruction(I, "swizzle");
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}
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@ -548,10 +558,10 @@ va_pack_load(const bi_instr *I, bool buffer_descriptor)
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if (!buffer_descriptor)
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hex |= va_pack_byte_offset(I);
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hex |= (uint64_t) va_pack_src(I->src[0]) << 0;
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hex |= (uint64_t) va_pack_src(I, 0) << 0;
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if (buffer_descriptor)
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hex |= (uint64_t) va_pack_src(I->src[1]) << 8;
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hex |= (uint64_t) va_pack_src(I, 1) << 8;
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return hex;
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}
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@ -573,7 +583,7 @@ va_pack_store(const bi_instr *I)
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uint64_t hex = va_pack_memory_access(I) << 24;
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va_validate_register_pair(I, 1);
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hex |= (uint64_t) va_pack_src(I->src[1]) << 0;
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hex |= (uint64_t) va_pack_src(I, 1) << 0;
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hex |= va_pack_byte_offset(I);
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@ -581,9 +591,9 @@ va_pack_store(const bi_instr *I)
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}
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static enum va_lod_mode
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va_pack_lod_mode(enum bi_va_lod_mode mode)
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va_pack_lod_mode(const bi_instr *I)
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{
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switch (mode) {
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switch (I->va_lod_mode) {
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case BI_VA_LOD_MODE_ZERO_LOD: return VA_LOD_MODE_ZERO;
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case BI_VA_LOD_MODE_COMPUTED_LOD: return VA_LOD_MODE_COMPUTED;
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case BI_VA_LOD_MODE_EXPLICIT: return VA_LOD_MODE_EXPLICIT;
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@ -591,13 +601,13 @@ va_pack_lod_mode(enum bi_va_lod_mode mode)
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case BI_VA_LOD_MODE_GRDESC: return VA_LOD_MODE_GRDESC;
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}
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unreachable("Invalid LOD mode");
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invalid_instruction(I, "LOD mode");
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}
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static enum va_register_type
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va_pack_register_type(enum bi_register_format regfmt)
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va_pack_register_type(const bi_instr *I)
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{
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switch (regfmt) {
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switch (I->register_format) {
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case BI_REGISTER_FORMAT_F16:
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case BI_REGISTER_FORMAT_F32:
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return VA_REGISTER_TYPE_F;
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@ -611,7 +621,7 @@ va_pack_register_type(enum bi_register_format regfmt)
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return VA_REGISTER_TYPE_S;
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default:
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unreachable("Invalid register format");
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invalid_instruction(I, "register type");
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}
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}
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||||
|
|
@ -707,18 +717,18 @@ va_pack_instr(const bi_instr *I)
|
|||
|
||||
/* 64-bit source */
|
||||
va_validate_register_pair(I, 0);
|
||||
hex |= (uint64_t) va_pack_src(I->src[0]) << 0;
|
||||
hex |= (uint64_t) va_pack_src(I, 0) << 0;
|
||||
hex |= va_pack_byte_offset_8(I);
|
||||
hex |= ((uint64_t) va_pack_atom_opc_1(I->atom_opc)) << 22;
|
||||
hex |= ((uint64_t) va_pack_atom_opc_1(I)) << 22;
|
||||
break;
|
||||
|
||||
case BI_OPCODE_ATOM_I32:
|
||||
case BI_OPCODE_ATOM_RETURN_I32:
|
||||
/* 64-bit source */
|
||||
va_validate_register_pair(I, 1);
|
||||
hex |= (uint64_t) va_pack_src(I->src[1]) << 0;
|
||||
hex |= (uint64_t) va_pack_src(I, 1) << 0;
|
||||
hex |= va_pack_byte_offset_8(I);
|
||||
hex |= ((uint64_t) va_pack_atom_opc(I->atom_opc)) << 22;
|
||||
hex |= ((uint64_t) va_pack_atom_opc(I)) << 22;
|
||||
|
||||
if (I->op == BI_OPCODE_ATOM_RETURN_I32)
|
||||
hex |= (0xc0ull << 40); // flags
|
||||
|
|
@ -733,13 +743,13 @@ va_pack_instr(const bi_instr *I)
|
|||
hex |= va_pack_store(I);
|
||||
|
||||
/* Conversion descriptor */
|
||||
hex |= (uint64_t) va_pack_src(I->src[3]) << 16;
|
||||
hex |= (uint64_t) va_pack_src(I, 3) << 16;
|
||||
break;
|
||||
|
||||
case BI_OPCODE_BLEND:
|
||||
{
|
||||
/* Source 0 - Blend descriptor (64-bit) */
|
||||
hex |= ((uint64_t) va_pack_src(I->src[2])) << 0;
|
||||
hex |= ((uint64_t) va_pack_src(I, 2)) << 0;
|
||||
va_validate_register_pair(I, 2);
|
||||
|
||||
/* Target */
|
||||
|
|
@ -761,7 +771,7 @@ va_pack_instr(const bi_instr *I)
|
|||
case BI_OPCODE_TEX_GATHER:
|
||||
{
|
||||
/* Image to read from */
|
||||
hex |= ((uint64_t) va_pack_src(I->src[1])) << 0;
|
||||
hex |= ((uint64_t) va_pack_src(I, 1)) << 0;
|
||||
|
||||
assert(!(I->op == BI_OPCODE_TEX_FETCH && I->shadow));
|
||||
|
||||
|
|
@ -771,10 +781,8 @@ va_pack_instr(const bi_instr *I)
|
|||
if (I->skip) hex |= (1ull << 39);
|
||||
if (!bi_is_regfmt_16(I->register_format)) hex |= (1ull << 46);
|
||||
|
||||
if (I->op == BI_OPCODE_TEX_SINGLE) {
|
||||
assert(I->va_lod_mode < 8);
|
||||
hex |= ((uint64_t) va_pack_lod_mode(I->va_lod_mode)) << 13;
|
||||
}
|
||||
if (I->op == BI_OPCODE_TEX_SINGLE)
|
||||
hex |= ((uint64_t) va_pack_lod_mode(I)) << 13;
|
||||
|
||||
if (I->op == BI_OPCODE_TEX_GATHER) {
|
||||
if (I->integer_coordinates) hex |= (1 << 13);
|
||||
|
|
@ -782,7 +790,7 @@ va_pack_instr(const bi_instr *I)
|
|||
}
|
||||
|
||||
hex |= (VA_WRITE_MASK_RGBA << 22);
|
||||
hex |= ((uint64_t) va_pack_register_type(I->register_format)) << 26;
|
||||
hex |= ((uint64_t) va_pack_register_type(I)) << 26;
|
||||
hex |= ((uint64_t) I->dimension) << 28;
|
||||
|
||||
break;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue