From cf7e1f3817d473f97427f7cf8b910b913c986227 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Fri, 5 Apr 2024 12:49:53 -0700 Subject: [PATCH] anv, iris: add missing CS_STALL bit for GPGPU texture invalidation The BSpec page "Flush Types" (46213) says the following about the Tex Invalidate bit: "Requires stall bit ([20] of DW) set for all GPGPU Workloads." For newer platforms, this is documented in the description of the texture invalidation bit in the PIPE_CONTROL page (56551): "CS Stall bit in PIPE_CONTROL command must be always set for GPGPU workloads when Texture Cache Invalidation Enable bit is set" Iris had it only for GFX_VER 9 and 11, while Anv had it missing for everything. Please notice that this patch includes a revert of 397e728ef4f1. Fixes: 397e728ef4f1 ("iris: Drop GPGPU Tex Invalidate restriction for TGL+") Reviewed-by: Lionel Landwerlin Reviewed-by: Nanley Chery Signed-off-by: Paulo Zanoni Part-of: --- src/gallium/drivers/iris/iris_state.c | 10 ++++++---- src/intel/vulkan/genX_cmd_buffer.c | 10 ++++++++++ 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index e00f55e1e9c..f32182fefe8 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -9764,10 +9764,12 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */ if (IS_COMPUTE_PIPELINE(batch)) { - if ((GFX_VER == 9 || GFX_VER == 11) && - (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) { - /* Project: SKL, ICL / Argument: Tex Invalidate - * "Requires stall bit ([20] of DW) set for all GPGPU Workloads." + if (GFX_VER >= 9 && (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) { + /* SKL PRMs, Volume 7: 3D-Media-GPGPU, Programming Restrictions for + * PIPE_CONTROL, Flush Types: + * "Requires stall bit ([20] of DW) set for all GPGPU Workloads." + * For newer platforms this is documented in the PIPE_CONTROL + * instruction page. */ flags |= PIPE_CONTROL_CS_STALL; } diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 119b9e53126..1f2d4710d11 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -2516,6 +2516,16 @@ genX(batch_emit_pipe_control_write)(struct anv_batch *batch, }; } + /* SKL PRMs, Volume 7: 3D-Media-GPGPU, Programming Restrictions for + * PIPE_CONTROL, Flush Types: + * "Requires stall bit ([20] of DW) set for all GPGPU Workloads." + * For newer platforms this is documented in the PIPE_CONTROL instruction + * page. + */ + if (current_pipeline == GPGPU && + (bits & ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT)) + bits |= ANV_PIPE_CS_STALL_BIT; + #if INTEL_NEEDS_WA_1409600907 /* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must * be set with any PIPE_CONTROL with Depth Flush Enable bit set.