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amd/common: unify PITCH_GFX6 and PITCH_GFX9

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The definition of the fields differs, but PITCH_GFX9 is a mere extension
of PITCH_GFX6 that does not conflict with any other fields.

This aligns the definitions with what will be generated from the
register JSON.

The information about how large the fields really are is preserved in
the register database.
This commit is contained in:
Nicolai Hähnle 2019-05-07 01:44:52 +02:00 • committed by Marek Olšák
parent e04215815e
commit cf51009ad2
5 changed files with 20 additions and 20 deletions
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6
src/amd/common/gfx9d.h
View file

@ -1446,9 +1446,9 @@
#define S_008F20_DEPTH(x) (((unsigned)(x) & 0x1FFF) << 0)
#define G_008F20_DEPTH(x) (((x) >> 0) & 0x1FFF)
#define C_008F20_DEPTH 0xFFFFE000
#define S_008F20_PITCH_GFX9(x) (((unsigned)(x) & 0xFFFF) << 13)
#define G_008F20_PITCH_GFX9(x) (((x) >> 13) & 0xFFFF)
#define C_008F20_PITCH_GFX9 0xE0001FFF
#define S_008F20_PITCH(x) (((unsigned)(x) & 0xFFFF) << 13)
#define G_008F20_PITCH(x) (((x) >> 13) & 0xFFFF)
#define C_008F20_PITCH 0xE0001FFF
#define S_008F20_BC_SWIZZLE(x) (((unsigned)(x) & 0x07) << 29)
#define G_008F20_BC_SWIZZLE(x) (((x) >> 29) & 0x07)
#define C_008F20_BC_SWIZZLE 0x1FFFFFFF

6
src/amd/common/sid.h
View file

@ -2326,9 +2326,9 @@
#define S_008F20_DEPTH(x) (((unsigned)(x) & 0x1FFF) << 0)
#define G_008F20_DEPTH(x) (((x) >> 0) & 0x1FFF)
#define C_008F20_DEPTH 0xFFFFE000
#define S_008F20_PITCH_GFX6(x) (((unsigned)(x) & 0x3FFF) << 13)
#define G_008F20_PITCH_GFX6(x) (((x) >> 13) & 0x3FFF)
#define C_008F20_PITCH_GFX6 0xF8001FFF
#define S_008F20_PITCH(x) (((unsigned)(x) & 0xFFFF) << 13)
#define G_008F20_PITCH(x) (((x) >> 13) & 0xFFFF)
#define C_008F20_PITCH 0xE0001FFF
#define R_008F24_SQ_IMG_RSRC_WORD5 0x008F24
#define S_008F24_BASE_ARRAY(x) (((unsigned)(x) & 0x1FFF) << 0)
#define G_008F24_BASE_ARRAY(x) (((x) >> 0) & 0x1FFF)

14
src/amd/vulkan/radv_image.c
View file

@ -398,14 +398,14 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
if (chip_class >= GFX9) {
state[3] &= C_008F1C_SW_MODE;
state[4] &= C_008F20_PITCH_GFX9;
state[4] &= C_008F20_PITCH;
if (is_stencil) {
state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
state[4] |= S_008F20_PITCH_GFX9(plane->surface.u.gfx9.stencil.epitch);
state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch);
} else {
state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
state[4] |= S_008F20_PITCH_GFX9(plane->surface.u.gfx9.surf.epitch);
state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch);
}
state[5] &= C_008F24_META_DATA_ADDRESS &
@ -430,8 +430,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
state[3] &= C_008F1C_TILING_INDEX;
state[3] |= S_008F1C_TILING_INDEX(index);
state[4] &= C_008F20_PITCH_GFX6;
state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
state[4] &= C_008F20_PITCH;
state[4] |= S_008F20_PITCH(pitch - 1);
}
}
@ -674,13 +674,13 @@ si_make_texture_descriptor(struct radv_device *device,
if (device->physical_device->rad_info.chip_class >= GFX9) {
fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
fmask_state[4] |= S_008F20_DEPTH(last_layer) |
S_008F20_PITCH_GFX9(image->planes[0].surface.u.gfx9.fmask.epitch);
S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
} else {
fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
}
} else if (fmask_state)

10
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -366,14 +366,14 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
if (sscreen->info.chip_class >= GFX9) {
state[3] &= C_008F1C_SW_MODE;
state[4] &= C_008F20_PITCH_GFX9;
state[4] &= C_008F20_PITCH;
if (is_stencil) {
state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
state[4] |= S_008F20_PITCH_GFX9(tex->surface.u.gfx9.stencil.epitch);
state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.stencil.epitch);
} else {
state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode);
state[4] |= S_008F20_PITCH_GFX9(tex->surface.u.gfx9.surf.epitch);
state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.surf.epitch);
}
state[5] &= C_008F24_META_DATA_ADDRESS &
@ -398,8 +398,8 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
state[3] &= C_008F1C_TILING_INDEX;
state[3] |= S_008F1C_TILING_INDEX(index);
state[4] &= C_008F20_PITCH_GFX6;
state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
state[4] &= C_008F20_PITCH;
state[4] |= S_008F20_PITCH(pitch - 1);
}
}

4
src/gallium/drivers/radeonsi/si_state.c
View file

@ -4023,13 +4023,13 @@ si_make_texture_descriptor(struct si_screen *screen,
if (screen->info.chip_class >= GFX9) {
fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
fmask_state[4] |= S_008F20_DEPTH(last_layer) |
S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
S_008F20_PITCH(tex->surface.u.gfx9.fmask.epitch);
fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
} else {
fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
S_008F20_PITCH_GFX6(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
S_008F20_PITCH(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
}
}