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https://gitlab.freedesktop.org/mesa/mesa.git
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nvfx: refactor shader assembler
This commit is contained in:
Luca Barbieri
parent
28fa9451e1
commit
cf0d156422
3 changed files with 355 additions and 358 deletions
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@ -20,8 +20,8 @@ struct nvfx_fpc {
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unsigned r_temps;
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unsigned r_temps_discard;
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struct nvfx_sreg r_result[PIPE_MAX_SHADER_OUTPUTS];
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struct nvfx_sreg *r_temp;
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struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS];
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struct nvfx_reg *r_temp;
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int num_regs;
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@ -34,13 +34,13 @@ struct nvfx_fpc {
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} consts[MAX_CONSTS];
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int nr_consts;
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struct nvfx_sreg imm[MAX_IMM];
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struct nvfx_reg imm[MAX_IMM];
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unsigned nr_imm;
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unsigned char generic_to_slot[256]; /* semantic idx for each input semantic */
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};
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static INLINE struct nvfx_sreg
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static INLINE struct nvfx_reg
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temp(struct nvfx_fpc *fpc)
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{
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int idx = ffs(~fpc->r_temps) - 1;
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@ -48,12 +48,12 @@ temp(struct nvfx_fpc *fpc)
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if (idx < 0) {
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NOUVEAU_ERR("out of temps!!\n");
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assert(0);
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return nvfx_sr(NVFXSR_TEMP, 0);
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return nvfx_reg(NVFXSR_TEMP, 0);
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}
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fpc->r_temps |= (1 << idx);
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fpc->r_temps_discard |= (1 << idx);
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return nvfx_sr(NVFXSR_TEMP, idx);
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return nvfx_reg(NVFXSR_TEMP, idx);
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}
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static INLINE void
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@ -63,7 +63,7 @@ release_temps(struct nvfx_fpc *fpc)
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fpc->r_temps_discard = 0;
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}
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static INLINE struct nvfx_sreg
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static INLINE struct nvfx_reg
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constant(struct nvfx_fpc *fpc, int pipe, float vals[4])
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{
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int idx;
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@ -75,16 +75,9 @@ constant(struct nvfx_fpc *fpc, int pipe, float vals[4])
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fpc->consts[idx].pipe = pipe;
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if (pipe == -1)
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memcpy(fpc->consts[idx].vals, vals, 4 * sizeof(float));
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return nvfx_sr(NVFXSR_CONST, idx);
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return nvfx_reg(NVFXSR_CONST, idx);
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}
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#define arith(cc,s,o,d,m,s0,s1,s2) \
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nvfx_fp_arith((cc), (s), NVFX_FP_OP_OPCODE_##o, \
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(d), (m), (s0), (s1), (s2))
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#define tex(cc,s,o,u,d,m,s0,s1,s2) \
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nvfx_fp_tex((cc), (s), NVFX_FP_OP_OPCODE_##o, (u), \
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(d), (m), (s0), none, none)
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static void
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grow_insns(struct nvfx_fpc *fpc, int size)
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{
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@ -95,28 +88,28 @@ grow_insns(struct nvfx_fpc *fpc, int size)
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}
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static void
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emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_sreg src)
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emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_src src)
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{
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struct nvfx_fragment_program *fp = fpc->fp;
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uint32_t *hw = &fp->insn[fpc->inst_offset];
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uint32_t sr = 0;
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switch (src.type) {
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switch (src.reg.type) {
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case NVFXSR_INPUT:
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sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
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hw[0] |= (src.index << NVFX_FP_OP_INPUT_SRC_SHIFT);
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hw[0] |= (src.reg.index << NVFX_FP_OP_INPUT_SRC_SHIFT);
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break;
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case NVFXSR_OUTPUT:
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sr |= NVFX_FP_REG_SRC_HALF;
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/* fall-through */
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case NVFXSR_TEMP:
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sr |= (NVFX_FP_REG_TYPE_TEMP << NVFX_FP_REG_TYPE_SHIFT);
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sr |= (src.index << NVFX_FP_REG_SRC_SHIFT);
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sr |= (src.reg.index << NVFX_FP_REG_SRC_SHIFT);
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break;
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case NVFXSR_RELOCATED:
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sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
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//printf("adding relocation at %x for %x\n", fpc->inst_offset, src.index);
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util_dynarray_append(&fpc->fp->slot_relocations[src.index], unsigned, fpc->inst_offset);
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util_dynarray_append(&fpc->fp->slot_relocations[src.reg.index], unsigned, fpc->inst_offset);
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break;
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case NVFXSR_CONST:
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if (!fpc->have_const) {
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@ -125,18 +118,18 @@ emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_sreg src)
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}
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hw = &fp->insn[fpc->inst_offset];
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if (fpc->consts[src.index].pipe >= 0) {
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if (fpc->consts[src.reg.index].pipe >= 0) {
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struct nvfx_fragment_program_data *fpd;
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fp->consts = realloc(fp->consts, ++fp->nr_consts *
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sizeof(*fpd));
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fpd = &fp->consts[fp->nr_consts - 1];
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fpd->offset = fpc->inst_offset + 4;
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fpd->index = fpc->consts[src.index].pipe;
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fpd->index = fpc->consts[src.reg.index].pipe;
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memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4);
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} else {
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memcpy(&fp->insn[fpc->inst_offset + 4],
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fpc->consts[src.index].vals,
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fpc->consts[src.reg.index].vals,
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sizeof(uint32_t) * 4);
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}
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@ -164,7 +157,7 @@ emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_sreg src)
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}
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static void
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emit_dst(struct nvfx_fpc *fpc, struct nvfx_sreg dst)
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emit_dst(struct nvfx_fpc *fpc, struct nvfx_reg dst)
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{
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struct nvfx_fragment_program *fp = fpc->fp;
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uint32_t *hw = &fp->insn[fpc->inst_offset];
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@ -192,9 +185,7 @@ emit_dst(struct nvfx_fpc *fpc, struct nvfx_sreg dst)
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}
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static void
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nvfx_fp_arith(struct nvfx_fpc *fpc, int sat, int op,
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struct nvfx_sreg dst, int mask,
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struct nvfx_sreg s0, struct nvfx_sreg s1, struct nvfx_sreg s2)
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nvfx_fp_emit(struct nvfx_fpc *fpc, struct nvfx_insn insn)
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{
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struct nvfx_fragment_program *fp = fpc->fp;
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uint32_t *hw;
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@ -205,85 +196,86 @@ nvfx_fp_arith(struct nvfx_fpc *fpc, int sat, int op,
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hw = &fp->insn[fpc->inst_offset];
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memset(hw, 0, sizeof(uint32_t) * 4);
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if (op == NVFX_FP_OP_OPCODE_KIL)
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if (insn.op == NVFX_FP_OP_OPCODE_KIL)
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fp->fp_control |= NV34TCL_FP_CONTROL_USES_KIL;
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hw[0] |= (op << NVFX_FP_OP_OPCODE_SHIFT);
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hw[0] |= (mask << NVFX_FP_OP_OUTMASK_SHIFT);
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hw[2] |= (dst.dst_scale << NVFX_FP_OP_DST_SCALE_SHIFT);
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hw[0] |= (insn.op << NVFX_FP_OP_OPCODE_SHIFT);
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hw[0] |= (insn.mask << NVFX_FP_OP_OUTMASK_SHIFT);
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hw[2] |= (insn.scale << NVFX_FP_OP_DST_SCALE_SHIFT);
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if (sat)
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if (insn.sat)
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hw[0] |= NVFX_FP_OP_OUT_SAT;
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if (dst.cc_update)
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if (insn.cc_update)
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hw[0] |= NVFX_FP_OP_COND_WRITE_ENABLE;
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hw[1] |= (dst.cc_test << NVFX_FP_OP_COND_SHIFT);
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hw[1] |= ((dst.cc_swz[0] << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
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(dst.cc_swz[1] << NVFX_FP_OP_COND_SWZ_Y_SHIFT) |
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(dst.cc_swz[2] << NVFX_FP_OP_COND_SWZ_Z_SHIFT) |
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(dst.cc_swz[3] << NVFX_FP_OP_COND_SWZ_W_SHIFT));
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hw[1] |= (insn.cc_test << NVFX_FP_OP_COND_SHIFT);
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hw[1] |= ((insn.cc_swz[0] << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
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(insn.cc_swz[1] << NVFX_FP_OP_COND_SWZ_Y_SHIFT) |
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(insn.cc_swz[2] << NVFX_FP_OP_COND_SWZ_Z_SHIFT) |
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(insn.cc_swz[3] << NVFX_FP_OP_COND_SWZ_W_SHIFT));
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emit_dst(fpc, dst);
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emit_src(fpc, 0, s0);
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emit_src(fpc, 1, s1);
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emit_src(fpc, 2, s2);
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if(insn.unit >= 0)
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{
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hw[0] |= (insn.unit << NVFX_FP_OP_TEX_UNIT_SHIFT);
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fp->samplers |= (1 << insn.unit);
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}
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emit_dst(fpc, insn.dst);
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emit_src(fpc, 0, insn.src[0]);
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emit_src(fpc, 1, insn.src[1]);
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emit_src(fpc, 2, insn.src[2]);
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}
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static void
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nvfx_fp_tex(struct nvfx_fpc *fpc, int sat, int op, int unit,
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struct nvfx_sreg dst, int mask,
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struct nvfx_sreg s0, struct nvfx_sreg s1, struct nvfx_sreg s2)
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{
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struct nvfx_fragment_program *fp = fpc->fp;
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#define arith(s,o,d,m,s0,s1,s2) \
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nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, -1, \
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(d), (m), (s0), (s1), (s2))
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nvfx_fp_arith(fpc, sat, op, dst, mask, s0, s1, s2);
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#define tex(s,o,u,d,m,s0,s1,s2) \
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nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, (u), \
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(d), (m), (s0), none, none)
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fp->insn[fpc->inst_offset] |= (unit << NVFX_FP_OP_TEX_UNIT_SHIFT);
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fp->samplers |= (1 << unit);
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}
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static INLINE struct nvfx_sreg
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static INLINE struct nvfx_src
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tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc)
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{
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struct nvfx_sreg src = { 0 };
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struct nvfx_src src;
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switch (fsrc->Register.File) {
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case TGSI_FILE_INPUT:
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if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_POSITION) {
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assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
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src = nvfx_sr(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_POSITION);
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src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_POSITION);
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} else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_COLOR) {
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if(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0)
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src = nvfx_sr(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL0);
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src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL0);
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else if(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 1)
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src = nvfx_sr(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL1);
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src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL1);
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else
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assert(0);
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} else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FOG) {
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assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
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src = nvfx_sr(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_FOGC);
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src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_FOGC);
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} else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FACE) {
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/* TODO: check this has the correct values */
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/* XXX: what do we do for nv30 here (assuming it lacks facing)?! */
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assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
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src = nvfx_sr(NVFXSR_INPUT, NV40_FP_OP_INPUT_SRC_FACING);
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src.reg = nvfx_reg(NVFXSR_INPUT, NV40_FP_OP_INPUT_SRC_FACING);
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} else {
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assert(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_GENERIC);
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src = nvfx_sr(NVFXSR_RELOCATED, fpc->generic_to_slot[fpc->fp->info.input_semantic_index[fsrc->Register.Index]]);
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src.reg = nvfx_reg(NVFXSR_RELOCATED, fpc->generic_to_slot[fpc->fp->info.input_semantic_index[fsrc->Register.Index]]);
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}
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break;
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case TGSI_FILE_CONSTANT:
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src = constant(fpc, fsrc->Register.Index, NULL);
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src.reg = constant(fpc, fsrc->Register.Index, NULL);
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break;
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case TGSI_FILE_IMMEDIATE:
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assert(fsrc->Register.Index < fpc->nr_imm);
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src = fpc->imm[fsrc->Register.Index];
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src.reg = fpc->imm[fsrc->Register.Index];
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break;
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case TGSI_FILE_TEMPORARY:
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src = fpc->r_temp[fsrc->Register.Index];
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src.reg = fpc->r_temp[fsrc->Register.Index];
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break;
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/* NV40 fragprog result regs are just temps, so this is simple */
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case TGSI_FILE_OUTPUT:
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src = fpc->r_result[fsrc->Register.Index];
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src.reg = fpc->r_result[fsrc->Register.Index];
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break;
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default:
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NOUVEAU_ERR("bad src file\n");
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@ -299,7 +291,7 @@ tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc)
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return src;
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}
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static INLINE struct nvfx_sreg
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static INLINE struct nvfx_reg
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tgsi_dst(struct nvfx_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
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switch (fdst->Register.File) {
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case TGSI_FILE_OUTPUT:
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@ -307,10 +299,10 @@ tgsi_dst(struct nvfx_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
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case TGSI_FILE_TEMPORARY:
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return fpc->r_temp[fdst->Register.Index];
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case TGSI_FILE_NULL:
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return nvfx_sr(NVFXSR_NONE, 0);
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return nvfx_reg(NVFXSR_NONE, 0);
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default:
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NOUVEAU_ERR("bad dst file %d\n", fdst->Register.File);
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return nvfx_sr(NVFXSR_NONE, 0);
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return nvfx_reg(NVFXSR_NONE, 0);
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}
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}
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@ -330,8 +322,10 @@ static boolean
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nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
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const struct tgsi_full_instruction *finst)
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{
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const struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
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struct nvfx_sreg src[3], dst, tmp;
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const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
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struct nvfx_insn insn;
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struct nvfx_src src[3], tmp;
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struct nvfx_reg dst;
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int mask, sat, unit = 0;
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int ai = -1, ci = -1, ii = -1;
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int i;
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@ -359,9 +353,8 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
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ai = fsrc->Register.Index;
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src[i] = tgsi_src(fpc, fsrc);
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} else {
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src[i] = temp(fpc);
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arith(fpc, 0, MOV, src[i], NVFX_FP_MASK_ALL,
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tgsi_src(fpc, fsrc), none, none);
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src[i] = nvfx_src(temp(fpc));
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nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
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}
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break;
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case TGSI_FILE_CONSTANT:
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@ -370,9 +363,8 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
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ci = fsrc->Register.Index;
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src[i] = tgsi_src(fpc, fsrc);
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} else {
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src[i] = temp(fpc);
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arith(fpc, 0, MOV, src[i], NVFX_FP_MASK_ALL,
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tgsi_src(fpc, fsrc), none, none);
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src[i] = nvfx_src(temp(fpc));
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nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
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}
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break;
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case TGSI_FILE_IMMEDIATE:
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@ -381,9 +373,8 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
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ii = fsrc->Register.Index;
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src[i] = tgsi_src(fpc, fsrc);
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} else {
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src[i] = temp(fpc);
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arith(fpc, 0, MOV, src[i], NVFX_FP_MASK_ALL,
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tgsi_src(fpc, fsrc), none, none);
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src[i] = nvfx_src(temp(fpc));
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nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
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}
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break;
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case TGSI_FILE_TEMPORARY:
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@ -406,227 +397,212 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
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switch (finst->Instruction.Opcode) {
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case TGSI_OPCODE_ABS:
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arith(fpc, sat, MOV, dst, mask, abs(src[0]), none, none);
|
||||
nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, abs(src[0]), none, none));
|
||||
break;
|
||||
case TGSI_OPCODE_ADD:
|
||||
arith(fpc, sat, ADD, dst, mask, src[0], src[1], none);
|
||||
nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_CMP:
|
||||
tmp = nvfx_sr(NVFXSR_NONE, 0);
|
||||
tmp.cc_update = 1;
|
||||
arith(fpc, 0, MOV, tmp, 0xf, src[0], none, none);
|
||||
dst.cc_test = NVFX_COND_GE;
|
||||
arith(fpc, sat, MOV, dst, mask, src[2], none, none);
|
||||
dst.cc_test = NVFX_COND_LT;
|
||||
arith(fpc, sat, MOV, dst, mask, src[1], none, none);
|
||||
insn = arith(0, MOV, none.reg, 0xf, src[0], none, none);
|
||||
insn.cc_update = 1;
|
||||
nvfx_fp_emit(fpc, insn);
|
||||
|
||||
insn = arith(sat, MOV, dst, mask, src[2], none, none);
|
||||
insn.cc_test = NVFX_COND_GE;
|
||||
nvfx_fp_emit(fpc, insn);
|
||||
|
||||
insn = arith(sat, MOV, dst, mask, src[1], none, none);
|
||||
insn.cc_test = NVFX_COND_LT;
|
||||
nvfx_fp_emit(fpc, insn);
|
||||
break;
|
||||
case TGSI_OPCODE_COS:
|
||||
arith(fpc, sat, COS, dst, mask, src[0], none, none);
|
||||
nvfx_fp_emit(fpc, arith(sat, COS, dst, mask, src[0], none, none));
|
||||
break;
|
||||
case TGSI_OPCODE_DDX:
|
||||
if (mask & (NVFX_FP_MASK_Z | NVFX_FP_MASK_W)) {
|
||||
tmp = temp(fpc);
|
||||
arith(fpc, sat, DDX, tmp, NVFX_FP_MASK_X | NVFX_FP_MASK_Y,
|
||||
swz(src[0], Z, W, Z, W), none, none);
|
||||
arith(fpc, 0, MOV, tmp, NVFX_FP_MASK_Z | NVFX_FP_MASK_W,
|
||||
swz(tmp, X, Y, X, Y), none, none);
|
||||
arith(fpc, sat, DDX, tmp, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0],
|
||||
none, none);
|
||||
arith(fpc, 0, MOV, dst, mask, tmp, none, none);
|
||||
tmp = nvfx_src(temp(fpc));
|
||||
nvfx_fp_emit(fpc, arith(sat, DDX, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, swz(src[0], Z, W, Z, W), none, none));
|
||||
nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_Z | NVFX_FP_MASK_W, swz(tmp, X, Y, X, Y), none, none));
|
||||
nvfx_fp_emit(fpc, arith(sat, DDX, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], none, none));
|
||||
nvfx_fp_emit(fpc, arith(0, MOV, dst, mask, tmp, none, none));
|
||||
} else {
|
||||
arith(fpc, sat, DDX, dst, mask, src[0], none, none);
|
||||
nvfx_fp_emit(fpc, arith(sat, DDX, dst, mask, src[0], none, none));
|
||||
}
|
||||
break;
|
||||
case TGSI_OPCODE_DDY:
|
||||
if (mask & (NVFX_FP_MASK_Z | NVFX_FP_MASK_W)) {
|
||||
tmp = temp(fpc);
|
||||
arith(fpc, sat, DDY, tmp, NVFX_FP_MASK_X | NVFX_FP_MASK_Y,
|
||||
swz(src[0], Z, W, Z, W), none, none);
|
||||
arith(fpc, 0, MOV, tmp, NVFX_FP_MASK_Z | NVFX_FP_MASK_W,
|
||||
swz(tmp, X, Y, X, Y), none, none);
|
||||
arith(fpc, sat, DDY, tmp, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0],
|
||||
none, none);
|
||||
arith(fpc, 0, MOV, dst, mask, tmp, none, none);
|
||||
tmp = nvfx_src(temp(fpc));
|
||||
nvfx_fp_emit(fpc, arith(sat, DDY, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, swz(src[0], Z, W, Z, W), none, none));
|
||||
nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_Z | NVFX_FP_MASK_W, swz(tmp, X, Y, X, Y), none, none));
|
||||
nvfx_fp_emit(fpc, arith(sat, DDY, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], none, none));
|
||||
nvfx_fp_emit(fpc, arith(0, MOV, dst, mask, tmp, none, none));
|
||||
} else {
|
||||
arith(fpc, sat, DDY, dst, mask, src[0], none, none);
|
||||
nvfx_fp_emit(fpc, arith(sat, DDY, dst, mask, src[0], none, none));
|
||||
}
|
||||
break;
|
||||
case TGSI_OPCODE_DP3:
|
||||
arith(fpc, sat, DP3, dst, mask, src[0], src[1], none);
|
||||
nvfx_fp_emit(fpc, arith(sat, DP3, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_DP4:
|
||||
arith(fpc, sat, DP4, dst, mask, src[0], src[1], none);
|
||||
nvfx_fp_emit(fpc, arith(sat, DP4, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_DPH:
|
||||
tmp = temp(fpc);
|
||||
arith(fpc, 0, DP3, tmp, NVFX_FP_MASK_X, src[0], src[1], none);
|
||||
arith(fpc, sat, ADD, dst, mask, swz(tmp, X, X, X, X),
|
||||
swz(src[1], W, W, W, W), none);
|
||||
tmp = nvfx_src(temp(fpc));
|
||||
nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_X, src[0], src[1], none));
|
||||
nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, swz(tmp, X, X, X, X), swz(src[1], W, W, W, W), none));
|
||||
break;
|
||||
case TGSI_OPCODE_DST:
|
||||
arith(fpc, sat, DST, dst, mask, src[0], src[1], none);
|
||||
nvfx_fp_emit(fpc, arith(sat, DST, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_EX2:
|
||||
arith(fpc, sat, EX2, dst, mask, src[0], none, none);
|
||||
nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, src[0], none, none));
|
||||
break;
|
||||
case TGSI_OPCODE_FLR:
|
||||
arith(fpc, sat, FLR, dst, mask, src[0], none, none);
|
||||
nvfx_fp_emit(fpc, arith(sat, FLR, dst, mask, src[0], none, none));
|
||||
break;
|
||||
case TGSI_OPCODE_FRC:
|
||||
arith(fpc, sat, FRC, dst, mask, src[0], none, none);
|
||||
nvfx_fp_emit(fpc, arith(sat, FRC, dst, mask, src[0], none, none));
|
||||
break;
|
||||
case TGSI_OPCODE_KILP:
|
||||
arith(fpc, 0, KIL, none, 0, none, none, none);
|
||||
nvfx_fp_emit(fpc, arith(0, KIL, none.reg, 0, none, none, none));
|
||||
break;
|
||||
case TGSI_OPCODE_KIL:
|
||||
dst = nvfx_sr(NVFXSR_NONE, 0);
|
||||
dst.cc_update = 1;
|
||||
arith(fpc, 0, MOV, dst, NVFX_FP_MASK_ALL, src[0], none, none);
|
||||
dst.cc_update = 0; dst.cc_test = NVFX_COND_LT;
|
||||
arith(fpc, 0, KIL, dst, 0, none, none, none);
|
||||
insn = arith(0, MOV, none.reg, NVFX_FP_MASK_ALL, src[0], none, none);
|
||||
insn.cc_update = 1;
|
||||
nvfx_fp_emit(fpc, insn);
|
||||
|
||||
insn = arith(0, KIL, none.reg, 0, none, none, none);
|
||||
insn.cc_test = NVFX_COND_LT;
|
||||
nvfx_fp_emit(fpc, insn);
|
||||
break;
|
||||
case TGSI_OPCODE_LG2:
|
||||
arith(fpc, sat, LG2, dst, mask, src[0], none, none);
|
||||
nvfx_fp_emit(fpc, arith(sat, LG2, dst, mask, src[0], none, none));
|
||||
break;
|
||||
// case TGSI_OPCODE_LIT:
|
||||
case TGSI_OPCODE_LRP:
|
||||
if(!nvfx->is_nv4x)
|
||||
arith(fpc, sat, LRP_NV30, dst, mask, src[0], src[1], src[2]);
|
||||
nvfx_fp_emit(fpc, arith(sat, LRP_NV30, dst, mask, src[0], src[1], src[2]));
|
||||
else {
|
||||
tmp = temp(fpc);
|
||||
arith(fpc, 0, MAD, tmp, mask, neg(src[0]), src[2], src[2]);
|
||||
arith(fpc, sat, MAD, dst, mask, src[0], src[1], tmp);
|
||||
tmp = nvfx_src(temp(fpc));
|
||||
nvfx_fp_emit(fpc, arith(0, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2]));
|
||||
nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, src[0], src[1], tmp));
|
||||
}
|
||||
break;
|
||||
case TGSI_OPCODE_MAD:
|
||||
arith(fpc, sat, MAD, dst, mask, src[0], src[1], src[2]);
|
||||
nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, src[0], src[1], src[2]));
|
||||
break;
|
||||
case TGSI_OPCODE_MAX:
|
||||
arith(fpc, sat, MAX, dst, mask, src[0], src[1], none);
|
||||
nvfx_fp_emit(fpc, arith(sat, MAX, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_MIN:
|
||||
arith(fpc, sat, MIN, dst, mask, src[0], src[1], none);
|
||||
nvfx_fp_emit(fpc, arith(sat, MIN, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_MOV:
|
||||
arith(fpc, sat, MOV, dst, mask, src[0], none, none);
|
||||
nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, src[0], none, none));
|
||||
break;
|
||||
case TGSI_OPCODE_MUL:
|
||||
arith(fpc, sat, MUL, dst, mask, src[0], src[1], none);
|
||||
nvfx_fp_emit(fpc, arith(sat, MUL, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_POW:
|
||||
if(!nvfx->is_nv4x)
|
||||
arith(fpc, sat, POW_NV30, dst, mask, src[0], src[1], none);
|
||||
nvfx_fp_emit(fpc, arith(sat, POW_NV30, dst, mask, src[0], src[1], none));
|
||||
else {
|
||||
tmp = temp(fpc);
|
||||
arith(fpc, 0, LG2, tmp, NVFX_FP_MASK_X,
|
||||
swz(src[0], X, X, X, X), none, none);
|
||||
arith(fpc, 0, MUL, tmp, NVFX_FP_MASK_X, swz(tmp, X, X, X, X),
|
||||
swz(src[1], X, X, X, X), none);
|
||||
arith(fpc, sat, EX2, dst, mask,
|
||||
swz(tmp, X, X, X, X), none, none);
|
||||
tmp = nvfx_src(temp(fpc));
|
||||
nvfx_fp_emit(fpc, arith(0, LG2, tmp.reg, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
|
||||
nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, NVFX_FP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none));
|
||||
nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, swz(tmp, X, X, X, X), none, none));
|
||||
}
|
||||
break;
|
||||
case TGSI_OPCODE_RCP:
|
||||
arith(fpc, sat, RCP, dst, mask, src[0], none, none);
|
||||
nvfx_fp_emit(fpc, arith(sat, RCP, dst, mask, src[0], none, none));
|
||||
break;
|
||||
case TGSI_OPCODE_RET:
|
||||
assert(0);
|
||||
break;
|
||||
case TGSI_OPCODE_RFL:
|
||||
if(!nvfx->is_nv4x)
|
||||
arith(fpc, 0, RFL_NV30, dst, mask, src[0], src[1], none);
|
||||
nvfx_fp_emit(fpc, arith(0, RFL_NV30, dst, mask, src[0], src[1], none));
|
||||
else {
|
||||
tmp = temp(fpc);
|
||||
arith(fpc, 0, DP3, tmp, NVFX_FP_MASK_X, src[0], src[0], none);
|
||||
arith(fpc, 0, DP3, tmp, NVFX_FP_MASK_Y, src[0], src[1], none);
|
||||
arith(fpc, 0, DIV, scale(tmp, 2X), NVFX_FP_MASK_Z,
|
||||
swz(tmp, Y, Y, Y, Y), swz(tmp, X, X, X, X), none);
|
||||
arith(fpc, sat, MAD, dst, mask,
|
||||
swz(tmp, Z, Z, Z, Z), src[0], neg(src[1]));
|
||||
tmp = nvfx_src(temp(fpc));
|
||||
nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_X, src[0], src[0], none));
|
||||
nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_Y, src[0], src[1], none));
|
||||
insn = arith(0, DIV, tmp.reg, NVFX_FP_MASK_Z, swz(tmp, Y, Y, Y, Y), swz(tmp, X, X, X, X), none);
|
||||
insn.scale = NVFX_FP_OP_DST_SCALE_2X;
|
||||
nvfx_fp_emit(fpc, insn);
|
||||
nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, swz(tmp, Z, Z, Z, Z), src[0], neg(src[1])));
|
||||
}
|
||||
break;
|
||||
case TGSI_OPCODE_RSQ:
|
||||
if(!nvfx->is_nv4x)
|
||||
arith(fpc, sat, RSQ_NV30, dst, mask, abs(swz(src[0], X, X, X, X)), none, none);
|
||||
nvfx_fp_emit(fpc, arith(sat, RSQ_NV30, dst, mask, abs(swz(src[0], X, X, X, X)), none, none));
|
||||
else {
|
||||
tmp = temp(fpc);
|
||||
arith(fpc, 0, LG2, scale(tmp, INV_2X), NVFX_FP_MASK_X,
|
||||
abs(swz(src[0], X, X, X, X)), none, none);
|
||||
arith(fpc, sat, EX2, dst, mask,
|
||||
neg(swz(tmp, X, X, X, X)), none, none);
|
||||
tmp = nvfx_src(temp(fpc));
|
||||
insn = arith(0, LG2, tmp.reg, NVFX_FP_MASK_X, abs(swz(src[0], X, X, X, X)), none, none);
|
||||
insn.scale = NVFX_FP_OP_DST_SCALE_INV_2X;
|
||||
nvfx_fp_emit(fpc, insn);
|
||||
nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, neg(swz(tmp, X, X, X, X)), none, none));
|
||||
}
|
||||
break;
|
||||
case TGSI_OPCODE_SCS:
|
||||
/* avoid overwriting the source */
|
||||
if(src[0].swz[NVFX_SWZ_X] != NVFX_SWZ_X)
|
||||
{
|
||||
if (mask & NVFX_FP_MASK_X) {
|
||||
arith(fpc, sat, COS, dst, NVFX_FP_MASK_X,
|
||||
swz(src[0], X, X, X, X), none, none);
|
||||
}
|
||||
if (mask & NVFX_FP_MASK_Y) {
|
||||
arith(fpc, sat, SIN, dst, NVFX_FP_MASK_Y,
|
||||
swz(src[0], X, X, X, X), none, none);
|
||||
}
|
||||
if (mask & NVFX_FP_MASK_X)
|
||||
nvfx_fp_emit(fpc, arith(sat, COS, dst, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
|
||||
if (mask & NVFX_FP_MASK_Y)
|
||||
nvfx_fp_emit(fpc, arith(sat, SIN, dst, NVFX_FP_MASK_Y, swz(src[0], X, X, X, X), none, none));
|
||||
}
|
||||
else
|
||||
{
|
||||
if (mask & NVFX_FP_MASK_Y) {
|
||||
arith(fpc, sat, SIN, dst, NVFX_FP_MASK_Y,
|
||||
swz(src[0], X, X, X, X), none, none);
|
||||
}
|
||||
if (mask & NVFX_FP_MASK_X) {
|
||||
arith(fpc, sat, COS, dst, NVFX_FP_MASK_X,
|
||||
swz(src[0], X, X, X, X), none, none);
|
||||
}
|
||||
if (mask & NVFX_FP_MASK_Y)
|
||||
nvfx_fp_emit(fpc, arith(sat, SIN, dst, NVFX_FP_MASK_Y, swz(src[0], X, X, X, X), none, none));
|
||||
if (mask & NVFX_FP_MASK_X)
|
||||
nvfx_fp_emit(fpc, arith(sat, COS, dst, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
|
||||
}
|
||||
break;
|
||||
case TGSI_OPCODE_SEQ:
|
||||
arith(fpc, sat, SEQ, dst, mask, src[0], src[1], none);
|
||||
nvfx_fp_emit(fpc, arith(sat, SEQ, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_SFL:
|
||||
arith(fpc, sat, SFL, dst, mask, src[0], src[1], none);
|
||||
nvfx_fp_emit(fpc, arith(sat, SFL, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_SGE:
|
||||
arith(fpc, sat, SGE, dst, mask, src[0], src[1], none);
|
||||
nvfx_fp_emit(fpc, arith(sat, SGE, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_SGT:
|
||||
arith(fpc, sat, SGT, dst, mask, src[0], src[1], none);
|
||||
nvfx_fp_emit(fpc, arith(sat, SGT, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_SIN:
|
||||
arith(fpc, sat, SIN, dst, mask, src[0], none, none);
|
||||
nvfx_fp_emit(fpc, arith(sat, SIN, dst, mask, src[0], none, none));
|
||||
break;
|
||||
case TGSI_OPCODE_SLE:
|
||||
arith(fpc, sat, SLE, dst, mask, src[0], src[1], none);
|
||||
nvfx_fp_emit(fpc, arith(sat, SLE, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_SLT:
|
||||
arith(fpc, sat, SLT, dst, mask, src[0], src[1], none);
|
||||
nvfx_fp_emit(fpc, arith(sat, SLT, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_SNE:
|
||||
arith(fpc, sat, SNE, dst, mask, src[0], src[1], none);
|
||||
nvfx_fp_emit(fpc, arith(sat, SNE, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_STR:
|
||||
arith(fpc, sat, STR, dst, mask, src[0], src[1], none);
|
||||
nvfx_fp_emit(fpc, arith(sat, STR, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_SUB:
|
||||
arith(fpc, sat, ADD, dst, mask, src[0], neg(src[1]), none);
|
||||
nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], neg(src[1]), none));
|
||||
break;
|
||||
case TGSI_OPCODE_TEX:
|
||||
tex(fpc, sat, TEX, unit, dst, mask, src[0], none, none);
|
||||
nvfx_fp_emit(fpc, tex(sat, TEX, unit, dst, mask, src[0], none, none));
|
||||
break;
|
||||
case TGSI_OPCODE_TXB:
|
||||
tex(fpc, sat, TXB, unit, dst, mask, src[0], none, none);
|
||||
nvfx_fp_emit(fpc, tex(sat, TXB, unit, dst, mask, src[0], none, none));
|
||||
break;
|
||||
case TGSI_OPCODE_TXP:
|
||||
tex(fpc, sat, TXP, unit, dst, mask, src[0], none, none);
|
||||
nvfx_fp_emit(fpc, tex(sat, TXP, unit, dst, mask, src[0], none, none));
|
||||
break;
|
||||
case TGSI_OPCODE_XPD:
|
||||
tmp = temp(fpc);
|
||||
arith(fpc, 0, MUL, tmp, mask,
|
||||
swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
|
||||
arith(fpc, sat, MAD, dst, (mask & ~NVFX_FP_MASK_W),
|
||||
swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
|
||||
neg(tmp));
|
||||
tmp = nvfx_src(temp(fpc));
|
||||
nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none));
|
||||
nvfx_fp_emit(fpc, arith(sat, MAD, dst, (mask & ~NVFX_FP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp)));
|
||||
break;
|
||||
default:
|
||||
NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
|
||||
|
|
@ -666,7 +642,7 @@ nvfx_fragprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
|
|||
return FALSE;
|
||||
}
|
||||
|
||||
fpc->r_result[idx] = nvfx_sr(NVFXSR_OUTPUT, hw);
|
||||
fpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw);
|
||||
fpc->r_temps |= (1 << hw);
|
||||
return TRUE;
|
||||
}
|
||||
|
|
@ -735,7 +711,7 @@ nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc)
|
|||
tgsi_parse_free(&p);
|
||||
|
||||
if (++high_temp) {
|
||||
fpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_sreg));
|
||||
fpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_reg));
|
||||
for (i = 0; i < high_temp; i++)
|
||||
fpc->r_temp[i] = temp(fpc);
|
||||
fpc->r_temps_discard = 0;
|
||||
|
|
|
|||
|
|
@ -405,51 +405,88 @@
|
|||
#define NVFX_SWZ_Z 2
|
||||
#define NVFX_SWZ_W 3
|
||||
|
||||
#define swz(s,x,y,z,w) nvfx_sr_swz((s), NVFX_SWZ_##x, NVFX_SWZ_##y, NVFX_SWZ_##z, NVFX_SWZ_##w)
|
||||
#define neg(s) nvfx_sr_neg((s))
|
||||
#define abs(s) nvfx_sr_abs((s))
|
||||
#define scale(s,v) nvfx_sr_scale((s), NVFX_FP_OP_DST_SCALE_##v)
|
||||
#define swz(s,x,y,z,w) nvfx_src_swz((s), NVFX_SWZ_##x, NVFX_SWZ_##y, NVFX_SWZ_##z, NVFX_SWZ_##w)
|
||||
#define neg(s) nvfx_src_neg((s))
|
||||
#define abs(s) nvfx_src_abs((s))
|
||||
|
||||
struct nvfx_sreg {
|
||||
int type;
|
||||
int index;
|
||||
|
||||
int dst_scale;
|
||||
|
||||
int negate;
|
||||
int abs;
|
||||
int swz[4];
|
||||
|
||||
int cc_update;
|
||||
int cc_update_reg;
|
||||
int cc_test;
|
||||
int cc_test_reg;
|
||||
int cc_swz[4];
|
||||
struct nvfx_reg {
|
||||
uint8_t type;
|
||||
uint32_t index;
|
||||
};
|
||||
|
||||
static INLINE struct nvfx_sreg
|
||||
nvfx_sr(int type, int index)
|
||||
struct nvfx_src {
|
||||
struct nvfx_reg reg;
|
||||
|
||||
/* src only */
|
||||
uint8_t negate : 1;
|
||||
uint8_t abs : 1;
|
||||
uint8_t swz[4];
|
||||
};
|
||||
|
||||
struct nvfx_insn
|
||||
{
|
||||
struct nvfx_sreg temp = {
|
||||
.type = type,
|
||||
.index = index,
|
||||
.dst_scale = 0,
|
||||
.abs = 0,
|
||||
.negate = 0,
|
||||
.swz = { 0, 1, 2, 3 },
|
||||
uint8_t op;
|
||||
char scale;
|
||||
int8_t unit;
|
||||
uint8_t mask;
|
||||
uint8_t cc_swz[4];
|
||||
|
||||
uint8_t sat : 1;
|
||||
uint8_t cc_update : 1;
|
||||
uint8_t cc_update_reg : 1;
|
||||
uint8_t cc_test : 3;
|
||||
uint8_t cc_test_reg : 1;
|
||||
|
||||
struct nvfx_reg dst;
|
||||
struct nvfx_src src[3];
|
||||
};
|
||||
|
||||
static INLINE struct nvfx_insn
|
||||
nvfx_insn(boolean sat, unsigned op, int unit, struct nvfx_reg dst, unsigned mask, struct nvfx_src s0, struct nvfx_src s1, struct nvfx_src s2)
|
||||
{
|
||||
struct nvfx_insn insn = {
|
||||
.op = op,
|
||||
.scale = 0,
|
||||
.unit = unit,
|
||||
.sat = sat,
|
||||
.mask = mask,
|
||||
.cc_update = 0,
|
||||
.cc_update_reg = 0,
|
||||
.cc_test = NVFX_COND_TR,
|
||||
.cc_test_reg = 0,
|
||||
.cc_swz = { 0, 1, 2, 3 },
|
||||
.dst = dst,
|
||||
.src = {s0, s1, s2}
|
||||
};
|
||||
return insn;
|
||||
}
|
||||
|
||||
static INLINE struct nvfx_reg
|
||||
nvfx_reg(int type, int index)
|
||||
{
|
||||
struct nvfx_reg temp = {
|
||||
.type = type,
|
||||
.index = index,
|
||||
};
|
||||
return temp;
|
||||
}
|
||||
|
||||
static INLINE struct nvfx_sreg
|
||||
nvfx_sr_swz(struct nvfx_sreg src, int x, int y, int z, int w)
|
||||
static INLINE struct nvfx_src
|
||||
nvfx_src(struct nvfx_reg reg)
|
||||
{
|
||||
struct nvfx_sreg dst = src;
|
||||
struct nvfx_src temp = {
|
||||
.reg = reg,
|
||||
.abs = 0,
|
||||
.negate = 0,
|
||||
.swz = { 0, 1, 2, 3 },
|
||||
};
|
||||
return temp;
|
||||
}
|
||||
|
||||
static INLINE struct nvfx_src
|
||||
nvfx_src_swz(struct nvfx_src src, int x, int y, int z, int w)
|
||||
{
|
||||
struct nvfx_src dst = src;
|
||||
|
||||
dst.swz[NVFX_SWZ_X] = src.swz[x];
|
||||
dst.swz[NVFX_SWZ_Y] = src.swz[y];
|
||||
|
|
@ -458,25 +495,18 @@ nvfx_sr_swz(struct nvfx_sreg src, int x, int y, int z, int w)
|
|||
return dst;
|
||||
}
|
||||
|
||||
static INLINE struct nvfx_sreg
|
||||
nvfx_sr_neg(struct nvfx_sreg src)
|
||||
static INLINE struct nvfx_src
|
||||
nvfx_src_neg(struct nvfx_src src)
|
||||
{
|
||||
src.negate = !src.negate;
|
||||
return src;
|
||||
}
|
||||
|
||||
static INLINE struct nvfx_sreg
|
||||
nvfx_sr_abs(struct nvfx_sreg src)
|
||||
static INLINE struct nvfx_src
|
||||
nvfx_src_abs(struct nvfx_src src)
|
||||
{
|
||||
src.abs = 1;
|
||||
return src;
|
||||
}
|
||||
|
||||
static INLINE struct nvfx_sreg
|
||||
nvfx_sr_scale(struct nvfx_sreg src, int scale)
|
||||
{
|
||||
src.dst_scale = scale;
|
||||
return src;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -30,23 +30,24 @@
|
|||
#define NVFX_VP_INST_DEST_CLIP(n) ((~0 - 6) + (n))
|
||||
|
||||
struct nvfx_vpc {
|
||||
struct nvfx_context* nvfx;
|
||||
struct nvfx_vertex_program *vp;
|
||||
|
||||
struct nvfx_vertex_program_exec *vpi;
|
||||
|
||||
unsigned r_temps;
|
||||
unsigned r_temps_discard;
|
||||
struct nvfx_sreg r_result[PIPE_MAX_SHADER_OUTPUTS];
|
||||
struct nvfx_sreg *r_address;
|
||||
struct nvfx_sreg *r_temp;
|
||||
struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS];
|
||||
struct nvfx_reg *r_address;
|
||||
struct nvfx_reg *r_temp;
|
||||
|
||||
struct nvfx_sreg *imm;
|
||||
struct nvfx_reg *imm;
|
||||
unsigned nr_imm;
|
||||
|
||||
unsigned hpos_idx;
|
||||
};
|
||||
|
||||
static struct nvfx_sreg
|
||||
static struct nvfx_reg
|
||||
temp(struct nvfx_vpc *vpc)
|
||||
{
|
||||
int idx = ffs(~vpc->r_temps) - 1;
|
||||
|
|
@ -54,12 +55,12 @@ temp(struct nvfx_vpc *vpc)
|
|||
if (idx < 0) {
|
||||
NOUVEAU_ERR("out of temps!!\n");
|
||||
assert(0);
|
||||
return nvfx_sr(NVFXSR_TEMP, 0);
|
||||
return nvfx_reg(NVFXSR_TEMP, 0);
|
||||
}
|
||||
|
||||
vpc->r_temps |= (1 << idx);
|
||||
vpc->r_temps_discard |= (1 << idx);
|
||||
return nvfx_sr(NVFXSR_TEMP, idx);
|
||||
return nvfx_reg(NVFXSR_TEMP, idx);
|
||||
}
|
||||
|
||||
static inline void
|
||||
|
|
@ -69,7 +70,7 @@ release_temps(struct nvfx_vpc *vpc)
|
|||
vpc->r_temps_discard = 0;
|
||||
}
|
||||
|
||||
static struct nvfx_sreg
|
||||
static struct nvfx_reg
|
||||
constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w)
|
||||
{
|
||||
struct nvfx_vertex_program *vp = vpc->vp;
|
||||
|
|
@ -79,7 +80,7 @@ constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w)
|
|||
if (pipe >= 0) {
|
||||
for (idx = 0; idx < vp->nr_consts; idx++) {
|
||||
if (vp->consts[idx].index == pipe)
|
||||
return nvfx_sr(NVFXSR_CONST, idx);
|
||||
return nvfx_reg(NVFXSR_CONST, idx);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -92,35 +93,35 @@ constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w)
|
|||
vpd->value[1] = y;
|
||||
vpd->value[2] = z;
|
||||
vpd->value[3] = w;
|
||||
return nvfx_sr(NVFXSR_CONST, idx);
|
||||
return nvfx_reg(NVFXSR_CONST, idx);
|
||||
}
|
||||
|
||||
#define arith(cc,s,o,d,m,s0,s1,s2) \
|
||||
nvfx_vp_arith(nvfx, (cc), NVFX_VP_INST_SLOT_##s, NVFX_VP_INST_##s##_OP_##o, (d), (m), (s0), (s1), (s2))
|
||||
#define arith(s,o,d,m,s0,s1,s2) \
|
||||
nvfx_insn(0, (NVFX_VP_INST_SLOT_##s << 7) | NVFX_VP_INST_##s##_OP_##o, -1, (d), (m), (s0), (s1), (s2))
|
||||
|
||||
static void
|
||||
emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos, struct nvfx_sreg src)
|
||||
emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos, struct nvfx_src src)
|
||||
{
|
||||
struct nvfx_vertex_program *vp = vpc->vp;
|
||||
uint32_t sr = 0;
|
||||
|
||||
switch (src.type) {
|
||||
switch (src.reg.type) {
|
||||
case NVFXSR_TEMP:
|
||||
sr |= (NVFX_VP(SRC_REG_TYPE_TEMP) << NVFX_VP(SRC_REG_TYPE_SHIFT));
|
||||
sr |= (src.index << NVFX_VP(SRC_TEMP_SRC_SHIFT));
|
||||
sr |= (src.reg.index << NVFX_VP(SRC_TEMP_SRC_SHIFT));
|
||||
break;
|
||||
case NVFXSR_INPUT:
|
||||
sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
|
||||
NVFX_VP(SRC_REG_TYPE_SHIFT));
|
||||
vp->ir |= (1 << src.index);
|
||||
hw[1] |= (src.index << NVFX_VP(INST_INPUT_SRC_SHIFT));
|
||||
vp->ir |= (1 << src.reg.index);
|
||||
hw[1] |= (src.reg.index << NVFX_VP(INST_INPUT_SRC_SHIFT));
|
||||
break;
|
||||
case NVFXSR_CONST:
|
||||
sr |= (NVFX_VP(SRC_REG_TYPE_CONST) <<
|
||||
NVFX_VP(SRC_REG_TYPE_SHIFT));
|
||||
assert(vpc->vpi->const_index == -1 ||
|
||||
vpc->vpi->const_index == src.index);
|
||||
vpc->vpi->const_index = src.index;
|
||||
vpc->vpi->const_index == src.reg.index);
|
||||
vpc->vpi->const_index = src.reg.index;
|
||||
break;
|
||||
case NVFXSR_NONE:
|
||||
sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
|
||||
|
|
@ -163,7 +164,7 @@ emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos,
|
|||
}
|
||||
|
||||
static void
|
||||
emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot, struct nvfx_sreg dst)
|
||||
emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot, struct nvfx_reg dst)
|
||||
{
|
||||
struct nvfx_vertex_program *vp = vpc->vp;
|
||||
|
||||
|
|
@ -173,13 +174,10 @@ emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot
|
|||
hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);
|
||||
else {
|
||||
hw[3] |= NV40_VP_INST_DEST_MASK;
|
||||
if (slot == 0) {
|
||||
hw[0] |= (dst.index <<
|
||||
NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
|
||||
} else {
|
||||
hw[3] |= (dst.index <<
|
||||
NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
|
||||
}
|
||||
if (slot == 0)
|
||||
hw[0] |= (dst.index << NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
|
||||
else
|
||||
hw[3] |= (dst.index << NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
|
||||
}
|
||||
break;
|
||||
case NVFXSR_OUTPUT:
|
||||
|
|
@ -279,12 +277,12 @@ emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot
|
|||
}
|
||||
|
||||
static void
|
||||
nvfx_vp_arith(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, int slot, int op,
|
||||
struct nvfx_sreg dst, int mask,
|
||||
struct nvfx_sreg s0, struct nvfx_sreg s1,
|
||||
struct nvfx_sreg s2)
|
||||
nvfx_vp_emit(struct nvfx_vpc *vpc, struct nvfx_insn insn)
|
||||
{
|
||||
struct nvfx_context* nvfx = vpc->nvfx;
|
||||
struct nvfx_vertex_program *vp = vpc->vp;
|
||||
unsigned slot = insn.op >> 7;
|
||||
unsigned op = insn.op & 0x7f;
|
||||
uint32_t *hw;
|
||||
|
||||
vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
|
||||
|
|
@ -311,51 +309,51 @@ nvfx_vp_arith(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, int slot, int op,
|
|||
// hw[3] |= NVFX_VP(INST_SCA_DEST_TEMP_MASK);
|
||||
// hw[3] |= (mask << NVFX_VP(INST_VEC_WRITEMASK_SHIFT));
|
||||
|
||||
if (dst.type == NVFXSR_OUTPUT) {
|
||||
if (insn.dst.type == NVFXSR_OUTPUT) {
|
||||
if (slot)
|
||||
hw[3] |= (mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
|
||||
hw[3] |= (insn.mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
|
||||
else
|
||||
hw[3] |= (mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
|
||||
hw[3] |= (insn.mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
|
||||
} else {
|
||||
if (slot)
|
||||
hw[3] |= (mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
|
||||
hw[3] |= (insn.mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
|
||||
else
|
||||
hw[3] |= (mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
|
||||
hw[3] |= (insn.mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
|
||||
}
|
||||
} else {
|
||||
if (slot == 0) {
|
||||
hw[1] |= (op << NV40_VP_INST_VEC_OPCODE_SHIFT);
|
||||
hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
|
||||
hw[3] |= (mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
|
||||
hw[3] |= (insn.mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
|
||||
} else {
|
||||
hw[1] |= (op << NV40_VP_INST_SCA_OPCODE_SHIFT);
|
||||
hw[0] |= (NV40_VP_INST_VEC_DEST_TEMP_MASK | (1 << 20));
|
||||
hw[3] |= (mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
|
||||
hw[3] |= (insn.mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
|
||||
}
|
||||
}
|
||||
|
||||
emit_dst(nvfx, vpc, hw, slot, dst);
|
||||
emit_src(nvfx, vpc, hw, 0, s0);
|
||||
emit_src(nvfx, vpc, hw, 1, s1);
|
||||
emit_src(nvfx, vpc, hw, 2, s2);
|
||||
emit_dst(nvfx, vpc, hw, slot, insn.dst);
|
||||
emit_src(nvfx, vpc, hw, 0, insn.src[0]);
|
||||
emit_src(nvfx, vpc, hw, 1, insn.src[1]);
|
||||
emit_src(nvfx, vpc, hw, 2, insn.src[2]);
|
||||
}
|
||||
|
||||
static inline struct nvfx_sreg
|
||||
static inline struct nvfx_src
|
||||
tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
|
||||
struct nvfx_sreg src = { 0 };
|
||||
struct nvfx_src src;
|
||||
|
||||
switch (fsrc->Register.File) {
|
||||
case TGSI_FILE_INPUT:
|
||||
src = nvfx_sr(NVFXSR_INPUT, fsrc->Register.Index);
|
||||
src.reg = nvfx_reg(NVFXSR_INPUT, fsrc->Register.Index);
|
||||
break;
|
||||
case TGSI_FILE_CONSTANT:
|
||||
src = constant(vpc, fsrc->Register.Index, 0, 0, 0, 0);
|
||||
src.reg = constant(vpc, fsrc->Register.Index, 0, 0, 0, 0);
|
||||
break;
|
||||
case TGSI_FILE_IMMEDIATE:
|
||||
src = vpc->imm[fsrc->Register.Index];
|
||||
src.reg = vpc->imm[fsrc->Register.Index];
|
||||
break;
|
||||
case TGSI_FILE_TEMPORARY:
|
||||
src = vpc->r_temp[fsrc->Register.Index];
|
||||
src.reg = vpc->r_temp[fsrc->Register.Index];
|
||||
break;
|
||||
default:
|
||||
NOUVEAU_ERR("bad src file\n");
|
||||
|
|
@ -371,9 +369,9 @@ tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
|
|||
return src;
|
||||
}
|
||||
|
||||
static INLINE struct nvfx_sreg
|
||||
static INLINE struct nvfx_reg
|
||||
tgsi_dst(struct nvfx_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
|
||||
struct nvfx_sreg dst = { 0 };
|
||||
struct nvfx_reg dst;
|
||||
|
||||
switch (fdst->Register.File) {
|
||||
case TGSI_FILE_OUTPUT:
|
||||
|
|
@ -409,8 +407,9 @@ static boolean
|
|||
nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
|
||||
const struct tgsi_full_instruction *finst)
|
||||
{
|
||||
struct nvfx_sreg src[3], dst, tmp;
|
||||
struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
|
||||
struct nvfx_src src[3], tmp;
|
||||
struct nvfx_reg dst;
|
||||
struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
|
||||
int mask;
|
||||
int ai = -1, ci = -1, ii = -1;
|
||||
int i;
|
||||
|
|
@ -438,9 +437,8 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
|
|||
ai = fsrc->Register.Index;
|
||||
src[i] = tgsi_src(vpc, fsrc);
|
||||
} else {
|
||||
src[i] = temp(vpc);
|
||||
arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
|
||||
tgsi_src(vpc, fsrc), none, none);
|
||||
src[i] = nvfx_src(temp(vpc));
|
||||
nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
|
||||
}
|
||||
break;
|
||||
case TGSI_FILE_CONSTANT:
|
||||
|
|
@ -449,9 +447,8 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
|
|||
ci = fsrc->Register.Index;
|
||||
src[i] = tgsi_src(vpc, fsrc);
|
||||
} else {
|
||||
src[i] = temp(vpc);
|
||||
arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
|
||||
tgsi_src(vpc, fsrc), none, none);
|
||||
src[i] = nvfx_src(temp(vpc));
|
||||
nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
|
||||
}
|
||||
break;
|
||||
case TGSI_FILE_IMMEDIATE:
|
||||
|
|
@ -460,9 +457,8 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
|
|||
ii = fsrc->Register.Index;
|
||||
src[i] = tgsi_src(vpc, fsrc);
|
||||
} else {
|
||||
src[i] = temp(vpc);
|
||||
arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
|
||||
tgsi_src(vpc, fsrc), none, none);
|
||||
src[i] = nvfx_src(temp(vpc));
|
||||
nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
|
||||
}
|
||||
break;
|
||||
case TGSI_FILE_TEMPORARY:
|
||||
|
|
@ -479,127 +475,121 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
|
|||
|
||||
switch (finst->Instruction.Opcode) {
|
||||
case TGSI_OPCODE_ABS:
|
||||
arith(vpc, VEC, MOV, dst, mask, abs(src[0]), none, none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, MOV, dst, mask, abs(src[0]), none, none));
|
||||
break;
|
||||
case TGSI_OPCODE_ADD:
|
||||
arith(vpc, VEC, ADD, dst, mask, src[0], none, src[1]);
|
||||
nvfx_vp_emit(vpc, arith(VEC, ADD, dst, mask, src[0], none, src[1]));
|
||||
break;
|
||||
case TGSI_OPCODE_ARL:
|
||||
arith(vpc, VEC, ARL, dst, mask, src[0], none, none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, ARL, dst, mask, src[0], none, none));
|
||||
break;
|
||||
case TGSI_OPCODE_COS:
|
||||
arith(vpc, SCA, COS, dst, mask, none, none, src[0]);
|
||||
nvfx_vp_emit(vpc, arith(SCA, COS, dst, mask, none, none, src[0]));
|
||||
break;
|
||||
case TGSI_OPCODE_DP3:
|
||||
arith(vpc, VEC, DP3, dst, mask, src[0], src[1], none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, DP3, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_DP4:
|
||||
arith(vpc, VEC, DP4, dst, mask, src[0], src[1], none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, DP4, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_DPH:
|
||||
arith(vpc, VEC, DPH, dst, mask, src[0], src[1], none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, DPH, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_DST:
|
||||
arith(vpc, VEC, DST, dst, mask, src[0], src[1], none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, DST, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_EX2:
|
||||
arith(vpc, SCA, EX2, dst, mask, none, none, src[0]);
|
||||
nvfx_vp_emit(vpc, arith(SCA, EX2, dst, mask, none, none, src[0]));
|
||||
break;
|
||||
case TGSI_OPCODE_EXP:
|
||||
arith(vpc, SCA, EXP, dst, mask, none, none, src[0]);
|
||||
nvfx_vp_emit(vpc, arith(SCA, EXP, dst, mask, none, none, src[0]));
|
||||
break;
|
||||
case TGSI_OPCODE_FLR:
|
||||
arith(vpc, VEC, FLR, dst, mask, src[0], none, none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, FLR, dst, mask, src[0], none, none));
|
||||
break;
|
||||
case TGSI_OPCODE_FRC:
|
||||
arith(vpc, VEC, FRC, dst, mask, src[0], none, none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, FRC, dst, mask, src[0], none, none));
|
||||
break;
|
||||
case TGSI_OPCODE_LG2:
|
||||
arith(vpc, SCA, LG2, dst, mask, none, none, src[0]);
|
||||
nvfx_vp_emit(vpc, arith(SCA, LG2, dst, mask, none, none, src[0]));
|
||||
break;
|
||||
case TGSI_OPCODE_LIT:
|
||||
arith(vpc, SCA, LIT, dst, mask, none, none, src[0]);
|
||||
nvfx_vp_emit(vpc, arith(SCA, LIT, dst, mask, none, none, src[0]));
|
||||
break;
|
||||
case TGSI_OPCODE_LOG:
|
||||
arith(vpc, SCA, LOG, dst, mask, none, none, src[0]);
|
||||
nvfx_vp_emit(vpc, arith(SCA, LOG, dst, mask, none, none, src[0]));
|
||||
break;
|
||||
case TGSI_OPCODE_LRP:
|
||||
tmp = temp(vpc);
|
||||
arith(vpc, VEC, MAD, tmp, mask, neg(src[0]), src[2], src[2]);
|
||||
arith(vpc, VEC, MAD, dst, mask, src[0], src[1], tmp);
|
||||
tmp = nvfx_src(temp(vpc));
|
||||
nvfx_vp_emit(vpc, arith(VEC, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2]));
|
||||
nvfx_vp_emit(vpc, arith(VEC, MAD, dst, mask, src[0], src[1], tmp));
|
||||
break;
|
||||
case TGSI_OPCODE_MAD:
|
||||
arith(vpc, VEC, MAD, dst, mask, src[0], src[1], src[2]);
|
||||
nvfx_vp_emit(vpc, arith(VEC, MAD, dst, mask, src[0], src[1], src[2]));
|
||||
break;
|
||||
case TGSI_OPCODE_MAX:
|
||||
arith(vpc, VEC, MAX, dst, mask, src[0], src[1], none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, MAX, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_MIN:
|
||||
arith(vpc, VEC, MIN, dst, mask, src[0], src[1], none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, MIN, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_MOV:
|
||||
arith(vpc, VEC, MOV, dst, mask, src[0], none, none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, MOV, dst, mask, src[0], none, none));
|
||||
break;
|
||||
case TGSI_OPCODE_MUL:
|
||||
arith(vpc, VEC, MUL, dst, mask, src[0], src[1], none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, MUL, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_POW:
|
||||
tmp = temp(vpc);
|
||||
arith(vpc, SCA, LG2, tmp, NVFX_VP_MASK_X, none, none,
|
||||
swz(src[0], X, X, X, X));
|
||||
arith(vpc, VEC, MUL, tmp, NVFX_VP_MASK_X, swz(tmp, X, X, X, X),
|
||||
swz(src[1], X, X, X, X), none);
|
||||
arith(vpc, SCA, EX2, dst, mask, none, none,
|
||||
swz(tmp, X, X, X, X));
|
||||
tmp = nvfx_src(temp(vpc));
|
||||
nvfx_vp_emit(vpc, arith(SCA, LG2, tmp.reg, NVFX_VP_MASK_X, none, none, swz(src[0], X, X, X, X)));
|
||||
nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, NVFX_VP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none));
|
||||
nvfx_vp_emit(vpc, arith(SCA, EX2, dst, mask, none, none, swz(tmp, X, X, X, X)));
|
||||
break;
|
||||
case TGSI_OPCODE_RCP:
|
||||
arith(vpc, SCA, RCP, dst, mask, none, none, src[0]);
|
||||
nvfx_vp_emit(vpc, arith(SCA, RCP, dst, mask, none, none, src[0]));
|
||||
break;
|
||||
case TGSI_OPCODE_RET:
|
||||
break;
|
||||
case TGSI_OPCODE_RSQ:
|
||||
arith(vpc, SCA, RSQ, dst, mask, none, none, abs(src[0]));
|
||||
nvfx_vp_emit(vpc, arith(SCA, RSQ, dst, mask, none, none, abs(src[0])));
|
||||
break;
|
||||
case TGSI_OPCODE_SEQ:
|
||||
arith(vpc, VEC, SEQ, dst, mask, src[0], src[1], none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, SEQ, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_SFL:
|
||||
arith(vpc, VEC, SFL, dst, mask, src[0], src[1], none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, SFL, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_SGE:
|
||||
arith(vpc, VEC, SGE, dst, mask, src[0], src[1], none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, SGE, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_SGT:
|
||||
arith(vpc, VEC, SGT, dst, mask, src[0], src[1], none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, SGT, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_SIN:
|
||||
arith(vpc, SCA, SIN, dst, mask, none, none, src[0]);
|
||||
nvfx_vp_emit(vpc, arith(SCA, SIN, dst, mask, none, none, src[0]));
|
||||
break;
|
||||
case TGSI_OPCODE_SLE:
|
||||
arith(vpc, VEC, SLE, dst, mask, src[0], src[1], none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, SLE, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_SLT:
|
||||
arith(vpc, VEC, SLT, dst, mask, src[0], src[1], none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, SLT, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_SNE:
|
||||
arith(vpc, VEC, SNE, dst, mask, src[0], src[1], none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, SNE, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_SSG:
|
||||
arith(vpc, VEC, SSG, dst, mask, src[0], src[1], none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, SSG, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_STR:
|
||||
arith(vpc, VEC, STR, dst, mask, src[0], src[1], none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, STR, dst, mask, src[0], src[1], none));
|
||||
break;
|
||||
case TGSI_OPCODE_SUB:
|
||||
arith(vpc, VEC, ADD, dst, mask, src[0], none, neg(src[1]));
|
||||
nvfx_vp_emit(vpc, arith(VEC, ADD, dst, mask, src[0], none, neg(src[1])));
|
||||
break;
|
||||
case TGSI_OPCODE_XPD:
|
||||
tmp = temp(vpc);
|
||||
arith(vpc, VEC, MUL, tmp, mask,
|
||||
swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
|
||||
arith(vpc, VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W),
|
||||
swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
|
||||
neg(tmp));
|
||||
tmp = nvfx_src(temp(vpc));
|
||||
nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none));
|
||||
nvfx_vp_emit(vpc, arith(VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp)));
|
||||
break;
|
||||
default:
|
||||
NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
|
||||
|
|
@ -663,7 +653,7 @@ nvfx_vertprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
|
|||
return FALSE;
|
||||
}
|
||||
|
||||
vpc->r_result[idx] = nvfx_sr(NVFXSR_OUTPUT, hw);
|
||||
vpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw);
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
|
@ -758,18 +748,18 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc)
|
|||
tgsi_parse_free(&p);
|
||||
|
||||
if (nr_imm) {
|
||||
vpc->imm = CALLOC(nr_imm, sizeof(struct nvfx_sreg));
|
||||
vpc->imm = CALLOC(nr_imm, sizeof(struct nvfx_reg));
|
||||
assert(vpc->imm);
|
||||
}
|
||||
|
||||
if (++high_temp) {
|
||||
vpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_sreg));
|
||||
vpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_reg));
|
||||
for (i = 0; i < high_temp; i++)
|
||||
vpc->r_temp[i] = temp(vpc);
|
||||
}
|
||||
|
||||
if (++high_addr) {
|
||||
vpc->r_address = CALLOC(high_addr, sizeof(struct nvfx_sreg));
|
||||
vpc->r_address = CALLOC(high_addr, sizeof(struct nvfx_reg));
|
||||
for (i = 0; i < high_addr; i++)
|
||||
vpc->r_address[i] = temp(vpc);
|
||||
}
|
||||
|
|
@ -786,12 +776,13 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
|
|||
{
|
||||
struct tgsi_parse_context parse;
|
||||
struct nvfx_vpc *vpc = NULL;
|
||||
struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
|
||||
struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
|
||||
int i;
|
||||
|
||||
vpc = CALLOC(1, sizeof(struct nvfx_vpc));
|
||||
if (!vpc)
|
||||
return;
|
||||
vpc->nvfx = nvfx;
|
||||
vpc->vp = vp;
|
||||
|
||||
if (!nvfx_vertprog_prepare(nvfx, vpc)) {
|
||||
|
|
@ -844,23 +835,23 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
|
|||
|
||||
/* Write out HPOS if it was redirected to a temp earlier */
|
||||
if (vpc->r_result[vpc->hpos_idx].type != NVFXSR_OUTPUT) {
|
||||
struct nvfx_sreg hpos = nvfx_sr(NVFXSR_OUTPUT,
|
||||
struct nvfx_reg hpos = nvfx_reg(NVFXSR_OUTPUT,
|
||||
NVFX_VP(INST_DEST_POS));
|
||||
struct nvfx_sreg htmp = vpc->r_result[vpc->hpos_idx];
|
||||
struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->hpos_idx]);
|
||||
|
||||
arith(vpc, VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none));
|
||||
}
|
||||
|
||||
/* Insert code to handle user clip planes */
|
||||
for (i = 0; i < vp->ucp.nr; i++) {
|
||||
struct nvfx_sreg cdst = nvfx_sr(NVFXSR_OUTPUT,
|
||||
struct nvfx_reg cdst = nvfx_reg(NVFXSR_OUTPUT,
|
||||
NVFX_VP_INST_DEST_CLIP(i));
|
||||
struct nvfx_sreg ceqn = constant(vpc, -1,
|
||||
struct nvfx_src ceqn = nvfx_src(constant(vpc, -1,
|
||||
nvfx->clip.ucp[i][0],
|
||||
nvfx->clip.ucp[i][1],
|
||||
nvfx->clip.ucp[i][2],
|
||||
nvfx->clip.ucp[i][3]);
|
||||
struct nvfx_sreg htmp = vpc->r_result[vpc->hpos_idx];
|
||||
nvfx->clip.ucp[i][3]));
|
||||
struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->hpos_idx]);
|
||||
unsigned mask;
|
||||
|
||||
switch (i) {
|
||||
|
|
@ -872,7 +863,7 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
|
|||
goto out_err;
|
||||
}
|
||||
|
||||
arith(vpc, VEC, DP4, cdst, mask, htmp, ceqn, none);
|
||||
nvfx_vp_emit(vpc, arith(VEC, DP4, cdst, mask, htmp, ceqn, none));
|
||||
}
|
||||
|
||||
vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue