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pan/mdg: remove register prefixes
Signed-off-by: Italo Nicola <italonicola@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9461>
This commit is contained in:
Italo Nicola
Marge Bot
parent
0ef3efb7fa
commit
cefa2e27da
1 changed files with 10 additions and 44 deletions
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@ -102,21 +102,6 @@ print_ld_st_opcode(FILE *fp, midgard_load_store_op op)
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fprintf(fp, "ldst_op_%02X", op);
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}
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static char
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prefix_for_bits(unsigned bits)
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{
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switch (bits) {
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case 8:
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return 'q';
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case 16:
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return 'h';
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case 64:
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return 'd';
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default:
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return 0;
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}
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}
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static void
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validate_expand_mode(midgard_src_expand_mode expand_mode,
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midgard_reg_mode reg_mode)
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@ -169,7 +154,7 @@ validate_expand_mode(midgard_src_expand_mode expand_mode,
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uint16_t midg_ever_written = 0;
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static void
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print_reg(FILE *fp, unsigned reg, unsigned bits)
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print_reg(FILE *fp, unsigned reg)
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{
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unsigned uniform_reg = 23 - reg;
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bool is_uniform = false;
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@ -192,11 +177,6 @@ print_reg(FILE *fp, unsigned reg, unsigned bits)
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midg_stats.uniform_count =
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MAX2(uniform_reg + 1, midg_stats.uniform_count);
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char prefix = prefix_for_bits(bits);
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if (prefix)
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fputc(prefix, fp);
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fprintf(fp, "r%u", reg);
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}
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@ -551,7 +531,7 @@ print_vector_src(FILE *fp, unsigned src_binary,
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validate_expand_mode(src->expand_mode, mode);
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print_reg(fp, reg, bits_for_mode_halved(mode, INPUT_EXPANDS(src->expand_mode)));
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print_reg(fp, reg);
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print_vec_swizzle(fp, src->swizzle, src->expand_mode, mode, src_mask);
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@ -590,19 +570,10 @@ update_dest(unsigned reg)
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}
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static void
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print_dest(FILE *fp, unsigned reg, midgard_reg_mode mode, midgard_shrink_mode shrink_mode)
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print_dest(FILE *fp, unsigned reg)
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{
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/* Depending on the lane width and shrink mode, we determine the type of
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* destination addressed. Absent a shrink mode, we address just the
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* type of the operation itself */
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unsigned bits = bits_for_mode(mode);
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if (shrink_mode != midgard_shrink_mode_none)
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bits /= 2;
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update_dest(reg);
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print_reg(fp, reg, bits);
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print_reg(fp, reg);
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}
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/* For 16-bit+ masks, we read off from the 8-bit mask field. For 16-bit (vec8),
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@ -713,7 +684,7 @@ print_vector_field(FILE *fp, const char *name, uint16_t *words, uint16_t reg_wor
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uint8_t mask = alu_field->mask;
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/* First, print the destination */
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print_dest(fp, reg_info->out_reg, mode, shrink_mode);
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print_dest(fp, reg_info->out_reg);
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if (shrink_mode != midgard_shrink_mode_none) {
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bool shrinkable = (mode != midgard_reg_mode_8);
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@ -775,7 +746,7 @@ print_scalar_src(FILE *fp, bool is_int, unsigned src_binary, unsigned reg)
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{
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midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
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print_reg(fp, reg, src->full ? 32 : 16);
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print_reg(fp, reg);
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unsigned c = src->component;
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@ -823,7 +794,7 @@ print_scalar_field(FILE *fp, const char *name, uint16_t *words, uint16_t reg_wor
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fprintf(fp, " ");
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update_dest(reg_info->out_reg);
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print_reg(fp, reg_info->out_reg, full ? 32 : 16);
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print_reg(fp, reg_info->out_reg);
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unsigned c = alu_field->output_component;
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if (full) {
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@ -1328,9 +1299,6 @@ print_texture_reg_select(FILE *fp, uint8_t u, unsigned base)
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midgard_tex_register_select sel;
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memcpy(&sel, &u, sizeof(u));
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if (!sel.full)
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fprintf(fp, "h");
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fprintf(fp, "r%u", base + sel.select);
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unsigned component = sel.component;
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@ -1512,8 +1480,7 @@ print_texture_word(FILE *fp, uint32_t *word, unsigned tabs, unsigned in_reg_base
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if (texture->out_of_order)
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fprintf(fp, ".ooo%u", texture->out_of_order);
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fprintf(fp, " %sr%u", texture->out_full ? "" : "h",
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out_reg_base + texture->out_reg_select);
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fprintf(fp, " r%u", out_reg_base + texture->out_reg_select);
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print_mask_4(fp, texture->mask, texture->out_upper);
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assert(!(texture->out_full && texture->out_upper));
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@ -1553,7 +1520,7 @@ print_texture_word(FILE *fp, uint32_t *word, unsigned tabs, unsigned in_reg_base
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}
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print_vec_swizzle(fp, texture->swizzle, midgard_src_passthrough, midgard_reg_mode_32, 0xFF);
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fprintf(fp, ", %sr%u", texture->in_reg_full ? "" : "h", in_reg_base + texture->in_reg_select);
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fprintf(fp, ", r%u", in_reg_base + texture->in_reg_select);
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assert(!(texture->in_reg_full && texture->in_reg_upper));
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midgard_src_expand_mode exp =
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@ -1573,14 +1540,13 @@ print_texture_word(FILE *fp, uint32_t *word, unsigned tabs, unsigned in_reg_base
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if (texture->offset_register) {
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fprintf(fp, " + ");
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bool full = texture->offset & 1;
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bool select = texture->offset & 2;
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bool upper = texture->offset & 4;
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unsigned swizzle = texture->offset >> 3;
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midgard_src_expand_mode exp =
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upper ? midgard_src_expand_high : midgard_src_passthrough;
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fprintf(fp, "%sr%u", full ? "" : "h", in_reg_base + select);
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fprintf(fp, "r%u", in_reg_base + select);
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print_vec_swizzle(fp, swizzle, exp, midgard_reg_mode_32, 0xFF);
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assert(!(texture->out_full && texture->out_upper));
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