From cec1024b22f132fa8148fc40d67f0b095a99faf7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 3 Apr 2026 14:32:21 -0400 Subject: [PATCH] ac,radv: remove AC_TRACKED_DB_VRS_OVERRIDE_CNTL as well AC_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL can be used instead because the DB and PA registers are mutually exclusive. 2 definitions are moved because consecutive enums aren't allowed to cross a multiple of 32 because of static assertions in the bitset. Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/common/ac_cmdbuf.c | 1 - src/amd/common/ac_cmdbuf.h | 9 ++++----- src/amd/vulkan/radv_cmd_buffer.c | 2 +- 3 files changed, 5 insertions(+), 7 deletions(-) diff --git a/src/amd/common/ac_cmdbuf.c b/src/amd/common/ac_cmdbuf.c index 8f2f69c92c8..998afa1afe0 100644 --- a/src/amd/common/ac_cmdbuf.c +++ b/src/amd/common/ac_cmdbuf.c @@ -873,7 +873,6 @@ ac_set_tracked_regs_to_clear_state(struct ac_tracked_regs *tracked_regs, tracked_regs->reg_value[AC_TRACKED_DB_STENCIL_CONTROL] = 0; tracked_regs->reg_value[AC_TRACKED_DB_DEPTH_BOUNDS_MIN] = 0; tracked_regs->reg_value[AC_TRACKED_DB_DEPTH_BOUNDS_MAX] = 0; - tracked_regs->reg_value[AC_TRACKED_DB_VRS_OVERRIDE_CNTL] = 0; tracked_regs->reg_value[AC_TRACKED_DB_ALPHA_TO_MASK] = 0; if (info->gfx_level >= GFX9) { diff --git a/src/amd/common/ac_cmdbuf.h b/src/amd/common/ac_cmdbuf.h index e5d78e5321c..ba3f182ea0b 100644 --- a/src/amd/common/ac_cmdbuf.h +++ b/src/amd/common/ac_cmdbuf.h @@ -117,7 +117,6 @@ enum ac_tracked_reg AC_TRACKED_DB_EQAA, AC_TRACKED_DB_RENDER_OVERRIDE2, AC_TRACKED_DB_SHADER_CONTROL, - AC_TRACKED_DB_VRS_OVERRIDE_CNTL, AC_TRACKED_DB_STENCIL_REF, AC_TRACKED_DB_ALPHA_TO_MASK, AC_TRACKED_CB_COLOR_CONTROL, @@ -243,15 +242,15 @@ enum ac_tracked_reg AC_TRACKED_COMPUTE_PGM_RSRC1, AC_TRACKED_COMPUTE_PGM_RSRC2, - /* 2 consecutive registers. */ - AC_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_LO, /* GFX11+ */ - AC_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_HI, /* GFX11+ */ - /* 3 consecutive registers. */ AC_TRACKED_SPI_SHADER_GS_MESHLET_DIM, /* GFX11+ */ AC_TRACKED_SPI_SHADER_GS_MESHLET_EXP_ALLOC, /* GFX11+ */ AC_TRACKED_SPI_SHADER_GS_MESHLET_CTRL, /* GFX12+ */ + /* 2 consecutive registers. */ + AC_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_LO, /* GFX11+ */ + AC_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_HI, /* GFX11+ */ + /* This spot is only for new SH and UCONFIG register enums. * Context register enums should be before AC_NUM_TRACKED_CONTEXT_REGS. */ diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index d0aaea095c5..3ea60bc681d 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -3903,7 +3903,7 @@ gfx103_emit_vrs_state(struct radv_cmd_buffer *cmd_buffer) } radeon_begin(cs); - radeon_opt_set_context_reg(R_028064_DB_VRS_OVERRIDE_CNTL, AC_TRACKED_DB_VRS_OVERRIDE_CNTL, + radeon_opt_set_context_reg(R_028064_DB_VRS_OVERRIDE_CNTL, AC_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(mode) | S_028064_VRS_OVERRIDE_RATE_X(rate_x) | S_028064_VRS_OVERRIDE_RATE_Y(rate_y)); radeon_end();