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intel/fs: roll the loop with the <0,1,0> additions in emit_scan()

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IMHO the code is easier to understand this way, being explicit that
we're doing exactly the same thing every time.

No functional changes.

v2: Adjust the loop breaking condition (Jason).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
This commit is contained in:
Paulo Zanoni 2019-08-23 17:15:27 -07:00 • committed by Jason Ekstrand
parent d9ddf5076d
commit cebf447d16
1 changed files with 14 additions and 32 deletions
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46
src/intel/compiler/brw_fs_builder.h
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@ -503,48 +503,30 @@ namespace brw {
}
}
if (cluster_size > 4) {
const fs_builder ubld = exec_all().group(4, 0);
src_reg left = component(tmp, 3);
dst_reg right = horiz_offset(tmp, 4);
for (unsigned i = 4;
i < MIN2(cluster_size, dispatch_width());
i *= 2) {
const fs_builder ubld = exec_all().group(i, 0);
src_reg left = component(tmp, i - 1);
dst_reg right = horiz_offset(tmp, i);
set_condmod(mod, ubld.emit(opcode, right, left, right));
if (dispatch_width() > 8) {
left = component(tmp, 8 + 3);
right = horiz_offset(tmp, 8 + 4);
if (dispatch_width() > i * 2) {
left = component(tmp, i * 3 - 1);
right = horiz_offset(tmp, i * 3);
set_condmod(mod, ubld.emit(opcode, right, left, right));
}
if (dispatch_width() > 16) {
left = component(tmp, 16 + 3);
right = horiz_offset(tmp, 16 + 4);
if (dispatch_width() > i * 4) {
left = component(tmp, i * 5 - 1);
right = horiz_offset(tmp, i * 5);
set_condmod(mod, ubld.emit(opcode, right, left, right));
left = component(tmp, 24 + 3);
right = horiz_offset(tmp, 24 + 4);
left = component(tmp, i * 7 - 1);
right = horiz_offset(tmp, i * 7);
set_condmod(mod, ubld.emit(opcode, right, left, right));
}
}
if (cluster_size > 8 && dispatch_width() > 8) {
const fs_builder ubld = exec_all().group(8, 0);
src_reg left = component(tmp, 7);
dst_reg right = horiz_offset(tmp, 8);
set_condmod(mod, ubld.emit(opcode, right, left, right));
if (dispatch_width() > 16) {
left = component(tmp, 16 + 7);
right = horiz_offset(tmp, 16 + 8);
set_condmod(mod, ubld.emit(opcode, right, left, right));
}
}
if (cluster_size > 16 && dispatch_width() > 16) {
const fs_builder ubld = exec_all().group(16, 0);
src_reg left = component(tmp, 15);
dst_reg right = horiz_offset(tmp, 16);
set_condmod(mod, ubld.emit(opcode, right, left, right));
}
}
/**