anv,blorp,isl: handle compressed CPS surfaces through the depth stencil hw

Compressed CPS surfaces operations such as copies and clears need to be
handled through the depth stencil hw to ensure that the aux data is
handled correctly.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20741>
This commit is contained in:
Rohan Garg 2025-01-30 16:47:19 +01:00 committed by Marge Bot
parent 6f4c23100a
commit ceba312ebd
2 changed files with 5 additions and 4 deletions

View file

@ -1892,7 +1892,8 @@ try_blorp_blit(struct blorp_batch *batch,
} else {
key->dst_usage = ISL_SURF_USAGE_RENDER_TARGET_BIT;
}
} else if (params->dst.surf.usage & ISL_SURF_USAGE_STENCIL_BIT) {
} else if (params->dst.surf.usage & (ISL_SURF_USAGE_STENCIL_BIT |
ISL_SURF_USAGE_CPB_BIT)) {
assert(params->dst.surf.format == ISL_FORMAT_R8_UINT);
if (devinfo->ver >= 9 && !(batch->flags & BLORP_BATCH_USE_COMPUTE)) {
key->dst_usage = ISL_SURF_USAGE_STENCIL_BIT;

View file

@ -99,7 +99,8 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
}
if (info->stencil_surf) {
assert((info->stencil_surf->usage & ISL_SURF_USAGE_STENCIL_BIT));
assert(info->stencil_surf->usage & (ISL_SURF_USAGE_STENCIL_BIT |
ISL_SURF_USAGE_CPB_BIT));
if (info->stencil_surf->dim == ISL_SURF_DIM_3D) {
assert(info->view->base_array_layer + info->view->array_len <=
info->stencil_surf->logical_level0_px.depth);
@ -264,9 +265,8 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
assert(info->stencil_aux_usage == ISL_AUX_USAGE_NONE ||
info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS);
#if GFX_VER < 20
sb.StencilCompressionEnable =
sb.ControlSurfaceEnable = sb.StencilCompressionEnable =
info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS;
sb.ControlSurfaceEnable = sb.StencilCompressionEnable;
#endif
#elif GFX_VERx10 >= 75
sb.StencilBufferEnable = true;