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i965: Rename CACHE_NEW_*_PROG to BRW_NEW_*_PROG_DATA.

Browse source 
Now that we've moved a bunch of CACHE_NEW_* bits to BRW_NEW_*, the only
ones that are left are legitimately related to the program cache.  Yet,
it seems a bit wasteful to have an entire bitfield for only 7 bits.

State upload is one of the hottest paths in the driver.  For each atom
in the list, we call check_state() to see if it needs to be emitted.
Currently, this involves comparing three separate bitfields (mesa, brw,
and cache).  Consolidating the brw and cache bitfields would save a
small amount of CPU overhead per atom.  Broadwell, for example, has
57 state atoms, so this small savings can add up.

CACHE_NEW_*_PROG covers the brw_*_prog_data structures, as well as the
offset into the program cache BO (prog_offset).  Since most uses refer
to brw_*_prog_data, I decided to use BRW_NEW_*_PROG_DATA as the name.

Removing "cache" completely is a bit painful, so I decided to do it in
several patches for easier review, and to separate mechanical changes
from manual ones.  This one simply renames things, and was made via:

$ for file in *.[ch]; do
      sed -i -e 's/CACHE_NEW_\([A-Z_\*]*\)_PROG/BRW_NEW_\1_PROG_DATA/g' \
             -e 's/BRW_NEW_WM_PROG_DATA/BRW_NEW_FS_PROG_DATA/g' $file
  done

Note that BRW_NEW_*_PROG_DATA is still in .cache, not .brw!
The next patch will remedy this flaw.  It will also fix the
alphabetization issues.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Kenneth Graunke 2014-11-24 23:30:51 -08:00
parent 2a4f5728ad
commit ce44b2061c
33 changed files with 124 additions and 124 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
src/mesa/drivers/dri/i965/brw_binding_tables.c
View file

@ -56,7 +56,7 @@ brw_upload_binding_table(struct brw_context *brw,
GLbitfield brw_new_binding_table,
struct brw_stage_state *stage_state)
{
/* CACHE_NEW_*_PROG */
/* BRW_NEW_*_PROG_DATA */
struct brw_stage_prog_data *prog_data = stage_state->prog_data;
if (prog_data->binding_table.size_bytes == 0) {
@ -112,7 +112,7 @@ const struct brw_tracked_state brw_vs_binding_table = {
.brw = BRW_NEW_BATCH |
BRW_NEW_VS_CONSTBUF |
BRW_NEW_SURFACES,
.cache = CACHE_NEW_VS_PROG
.cache = BRW_NEW_VS_PROG_DATA
},
.emit = brw_vs_upload_binding_table,
};
@ -132,7 +132,7 @@ const struct brw_tracked_state brw_wm_binding_table = {
.mesa = 0,
.brw = BRW_NEW_BATCH |
BRW_NEW_SURFACES,
.cache = CACHE_NEW_WM_PROG
.cache = BRW_NEW_FS_PROG_DATA
},
.emit = brw_upload_wm_binding_table,
};
@ -156,7 +156,7 @@ const struct brw_tracked_state brw_gs_binding_table = {
.brw = BRW_NEW_BATCH |
BRW_NEW_GS_CONSTBUF |
BRW_NEW_SURFACES,
.cache = CACHE_NEW_GS_PROG
.cache = BRW_NEW_GS_PROG_DATA
},
.emit = brw_gs_upload_binding_table,
};

4
src/mesa/drivers/dri/i965/brw_clip_state.c
View file

@ -67,7 +67,7 @@ brw_upload_clip_unit(struct brw_context *brw)
sizeof(*clip), 32, &brw->clip.state_offset);
memset(clip, 0, sizeof(*clip));
/* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_CLIP_PROG */
/* BRW_NEW_PROGRAM_CACHE | BRW_NEW_CLIP_PROG_DATA */
clip->thread0.grf_reg_count = (ALIGN(brw->clip.prog_data->total_grf, 16) /
16 - 1);
clip->thread0.kernel_start_pointer =
@ -170,7 +170,7 @@ const struct brw_tracked_state brw_clip_unit = {
BRW_NEW_CURBE_OFFSETS |
BRW_NEW_PROGRAM_CACHE |
BRW_NEW_URB_FENCE,
.cache = CACHE_NEW_CLIP_PROG
.cache = BRW_NEW_CLIP_PROG_DATA
},
.emit = brw_upload_clip_unit,
};

16
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -248,7 +248,7 @@ struct brw_state_flags {
*
* Now almost all of that state is just streamed out on demand, but the
* flags for those state blobs updating have stayed in the same bitfield.
* brw_state_cache.c still flags CACHE_NEW_*_PROG.
* brw_state_cache.c still flags BRW_NEW_*_PROG_DATA.
*/
GLuint cache;
};
@ -777,13 +777,13 @@ enum shader_time_shader_type {
/* Flags for brw->state.cache.
*/
#define CACHE_NEW_WM_PROG (1 << BRW_CACHE_FS_PROG)
#define CACHE_NEW_BLORP_BLIT_PROG (1 << BRW_CACHE_BLORP_BLIT_PROG)
#define CACHE_NEW_SF_PROG (1 << BRW_CACHE_SF_PROG)
#define CACHE_NEW_VS_PROG (1 << BRW_CACHE_VS_PROG)
#define CACHE_NEW_FF_GS_PROG (1 << BRW_CACHE_FF_GS_PROG)
#define CACHE_NEW_GS_PROG (1 << BRW_CACHE_GS_PROG)
#define CACHE_NEW_CLIP_PROG (1 << BRW_CACHE_CLIP_PROG)
#define BRW_NEW_FS_PROG_DATA (1 << BRW_CACHE_FS_PROG)
#define BRW_NEW_BLORP_BLIT_PROG_DATA (1 << BRW_CACHE_BLORP_BLIT_PROG)
#define BRW_NEW_SF_PROG_DATA (1 << BRW_CACHE_SF_PROG)
#define BRW_NEW_VS_PROG_DATA (1 << BRW_CACHE_VS_PROG)
#define BRW_NEW_FF_GS_PROG_DATA (1 << BRW_CACHE_FF_GS_PROG)
#define BRW_NEW_GS_PROG_DATA (1 << BRW_CACHE_GS_PROG)
#define BRW_NEW_CLIP_PROG_DATA (1 << BRW_CACHE_CLIP_PROG)
struct brw_vertex_buffer {
/** Buffer object containing the uploaded vertex data */

16
src/mesa/drivers/dri/i965/brw_curbe.c
View file

@ -75,10 +75,10 @@
static void calculate_curbe_offsets( struct brw_context *brw )
{
struct gl_context *ctx = &brw->ctx;
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
const GLuint nr_fp_regs = (brw->wm.prog_data->base.nr_params + 15) / 16;
/* CACHE_NEW_VS_PROG */
/* BRW_NEW_VS_PROG_DATA */
const GLuint nr_vp_regs = (brw->vs.prog_data->base.base.nr_params + 15) / 16;
GLuint nr_clip_regs = 0;
GLuint total_regs;
@ -143,8 +143,8 @@ const struct brw_tracked_state brw_curbe_offsets = {
.dirty = {
.mesa = _NEW_TRANSFORM,
.brw = BRW_NEW_CONTEXT,
.cache = CACHE_NEW_VS_PROG |
CACHE_NEW_WM_PROG
.cache = BRW_NEW_VS_PROG_DATA |
BRW_NEW_FS_PROG_DATA
},
.emit = calculate_curbe_offsets
};
@ -217,7 +217,7 @@ brw_upload_constant_buffer(struct brw_context *brw)
/* BRW_NEW_CURBE_OFFSETS */
GLuint offset = brw->curbe.wm_start * 16;
/* CACHE_NEW_WM_PROG | _NEW_PROGRAM_CONSTANTS: copy uniform values */
/* BRW_NEW_FS_PROG_DATA | _NEW_PROGRAM_CONSTANTS: copy uniform values */
for (i = 0; i < brw->wm.prog_data->base.nr_params; i++) {
buf[offset + i] = *brw->wm.prog_data->base.param[i];
}
@ -258,7 +258,7 @@ brw_upload_constant_buffer(struct brw_context *brw)
GLuint offset = brw->curbe.vs_start * 16;
/* CACHE_NEW_VS_PROG | _NEW_PROGRAM_CONSTANTS: copy uniform values */
/* BRW_NEW_VS_PROG_DATA | _NEW_PROGRAM_CONSTANTS: copy uniform values */
for (i = 0; i < brw->vs.prog_data->base.base.nr_params; i++) {
buf[offset + i] = *brw->vs.prog_data->base.base.param[i];
}
@ -313,8 +313,8 @@ const struct brw_tracked_state brw_constant_buffer = {
BRW_NEW_CURBE_OFFSETS |
BRW_NEW_PSP | /* Implicit - hardware requires this, not used above */
BRW_NEW_URB_FENCE,
.cache = CACHE_NEW_VS_PROG |
CACHE_NEW_WM_PROG
.cache = BRW_NEW_VS_PROG_DATA |
BRW_NEW_FS_PROG_DATA
},
.emit = brw_upload_constant_buffer,
};

4
src/mesa/drivers/dri/i965/brw_draw_upload.c
View file

@ -400,7 +400,7 @@ void
brw_prepare_vertices(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
/* CACHE_NEW_VS_PROG */
/* BRW_NEW_VS_PROG_DATA */
GLbitfield64 vs_inputs = brw->vs.prog_data->inputs_read;
const unsigned char *ptr = NULL;
GLuint interleaved = 0;
@ -871,7 +871,7 @@ const struct brw_tracked_state brw_vertices = {
.mesa = _NEW_POLYGON,
.brw = BRW_NEW_BATCH |
BRW_NEW_VERTICES,
.cache = CACHE_NEW_VS_PROG,
.cache = BRW_NEW_VS_PROG_DATA,
},
.emit = brw_emit_vertices,
};

6
src/mesa/drivers/dri/i965/brw_ff_gs.c
View file

@ -161,7 +161,7 @@ static void populate_key(struct brw_context *brw,
memset(key, 0, sizeof(*key));
/* CACHE_NEW_VS_PROG (part of VUE map) */
/* BRW_NEW_VS_PROG_DATA (part of VUE map) */
key->attrs = brw->vs.prog_data->base.vue_map.slots_valid;
/* BRW_NEW_PRIMITIVE */
@ -230,7 +230,7 @@ brw_upload_ff_gs_prog(struct brw_context *brw)
populate_key(brw, &key);
if (brw->ff_gs.prog_active != key.need_gs_prog) {
brw->state.dirty.cache |= CACHE_NEW_FF_GS_PROG;
brw->state.dirty.cache |= BRW_NEW_FF_GS_PROG_DATA;
brw->ff_gs.prog_active = key.need_gs_prog;
}
@ -253,7 +253,7 @@ const struct brw_tracked_state brw_ff_gs_prog = {
.mesa = _NEW_LIGHT,
.brw = BRW_NEW_PRIMITIVE |
BRW_NEW_TRANSFORM_FEEDBACK,
.cache = CACHE_NEW_VS_PROG
.cache = BRW_NEW_VS_PROG_DATA
},
.emit = brw_upload_ff_gs_prog
};

4
src/mesa/drivers/dri/i965/brw_gs_state.c
View file

@ -45,7 +45,7 @@ brw_upload_gs_unit(struct brw_context *brw)
memset(gs, 0, sizeof(*gs));
/* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_GS_PROG */
/* BRW_NEW_PROGRAM_CACHE | BRW_NEW_GS_PROG_DATA */
if (brw->ff_gs.prog_active) {
gs->thread0.grf_reg_count = (ALIGN(brw->ff_gs.prog_data->total_grf, 16) /
16 - 1);
@ -95,7 +95,7 @@ const struct brw_tracked_state brw_gs_unit = {
BRW_NEW_CURBE_OFFSETS |
BRW_NEW_PROGRAM_CACHE |
BRW_NEW_URB_FENCE,
.cache = CACHE_NEW_FF_GS_PROG
.cache = BRW_NEW_FF_GS_PROG_DATA
},
.emit = brw_upload_gs_unit,
};

12
src/mesa/drivers/dri/i965/brw_gs_surface_state.c
View file

@ -46,7 +46,7 @@ brw_upload_gs_pull_constants(struct brw_context *brw)
if (!gp)
return;
/* CACHE_NEW_GS_PROG */
/* BRW_NEW_GS_PROG_DATA */
const struct brw_stage_prog_data *prog_data = &brw->gs.prog_data->base.base;
/* _NEW_PROGRAM_CONSTANTS */
@ -59,7 +59,7 @@ const struct brw_tracked_state brw_gs_pull_constants = {
.mesa = _NEW_PROGRAM_CONSTANTS,
.brw = BRW_NEW_BATCH |
BRW_NEW_GEOMETRY_PROGRAM,
.cache = CACHE_NEW_GS_PROG,
.cache = BRW_NEW_GS_PROG_DATA,
},
.emit = brw_upload_gs_pull_constants,
};
@ -76,7 +76,7 @@ brw_upload_gs_ubo_surfaces(struct brw_context *brw)
if (!prog)
return;
/* CACHE_NEW_GS_PROG */
/* BRW_NEW_GS_PROG_DATA */
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_GEOMETRY],
&brw->gs.base, &brw->gs.prog_data->base.base);
}
@ -86,7 +86,7 @@ const struct brw_tracked_state brw_gs_ubo_surfaces = {
.mesa = _NEW_PROGRAM,
.brw = BRW_NEW_BATCH |
BRW_NEW_UNIFORM_BUFFER,
.cache = CACHE_NEW_GS_PROG,
.cache = BRW_NEW_GS_PROG_DATA,
},
.emit = brw_upload_gs_ubo_surfaces,
};
@ -100,7 +100,7 @@ brw_upload_gs_abo_surfaces(struct brw_context *brw)
ctx->_Shader->CurrentProgram[MESA_SHADER_GEOMETRY];
if (prog) {
/* CACHE_NEW_GS_PROG */
/* BRW_NEW_GS_PROG_DATA */
brw_upload_abo_surfaces(brw, prog, &brw->gs.base,
&brw->gs.prog_data->base.base);
}
@ -111,7 +111,7 @@ const struct brw_tracked_state brw_gs_abo_surfaces = {
.mesa = _NEW_PROGRAM,
.brw = BRW_NEW_ATOMIC_BUFFER |
BRW_NEW_BATCH,
.cache = CACHE_NEW_GS_PROG,
.cache = BRW_NEW_GS_PROG_DATA,
},
.emit = brw_upload_gs_abo_surfaces,
};

2
src/mesa/drivers/dri/i965/brw_misc_state.c
View file

@ -120,7 +120,7 @@ const struct brw_tracked_state brw_psp_urb_cbs = {
BRW_NEW_GEN4_UNIT_STATE |
BRW_NEW_STATE_BASE_ADDRESS |
BRW_NEW_URB_FENCE,
.cache = CACHE_NEW_FF_GS_PROG,
.cache = BRW_NEW_FF_GS_PROG_DATA,
},
.emit = upload_psp_urb_cbs,
};

6
src/mesa/drivers/dri/i965/brw_sf_state.c
View file

@ -136,7 +136,7 @@ static void upload_sf_unit( struct brw_context *brw )
memset(sf, 0, sizeof(*sf));
/* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_SF_PROG */
/* BRW_NEW_PROGRAM_CACHE | BRW_NEW_SF_PROG_DATA */
sf->thread0.grf_reg_count = ALIGN(brw->sf.prog_data->total_grf, 16) / 16 - 1;
sf->thread0.kernel_start_pointer =
brw_program_reloc(brw,
@ -150,7 +150,7 @@ static void upload_sf_unit( struct brw_context *brw )
sf->thread3.dispatch_grf_start_reg = 3;
sf->thread3.urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET;
/* CACHE_NEW_SF_PROG */
/* BRW_NEW_SF_PROG_DATA */
sf->thread3.urb_entry_read_length = brw->sf.prog_data->urb_read_length;
/* BRW_NEW_URB_FENCE */
@ -308,7 +308,7 @@ const struct brw_tracked_state brw_sf_unit = {
BRW_NEW_PROGRAM_CACHE |
BRW_NEW_SF_VP |
BRW_NEW_URB_FENCE,
.cache = CACHE_NEW_SF_PROG,
.cache = BRW_NEW_SF_PROG_DATA,
},
.emit = upload_sf_unit,
};

14
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -528,13 +528,13 @@ static struct dirty_bit_map brw_bits[] = {
};
static struct dirty_bit_map cache_bits[] = {
DEFINE_BIT(CACHE_NEW_WM_PROG),
DEFINE_BIT(CACHE_NEW_BLORP_BLIT_PROG),
DEFINE_BIT(CACHE_NEW_SF_PROG),
DEFINE_BIT(CACHE_NEW_VS_PROG),
DEFINE_BIT(CACHE_NEW_FF_GS_PROG),
DEFINE_BIT(CACHE_NEW_GS_PROG),
DEFINE_BIT(CACHE_NEW_CLIP_PROG),
DEFINE_BIT(BRW_NEW_FS_PROG_DATA),
DEFINE_BIT(BRW_NEW_BLORP_BLIT_PROG_DATA),
DEFINE_BIT(BRW_NEW_SF_PROG_DATA),
DEFINE_BIT(BRW_NEW_VS_PROG_DATA),
DEFINE_BIT(BRW_NEW_FF_GS_PROG_DATA),
DEFINE_BIT(BRW_NEW_GS_PROG_DATA),
DEFINE_BIT(BRW_NEW_CLIP_PROG_DATA),
{0, 0, 0}
};

4
src/mesa/drivers/dri/i965/brw_urb.c
View file

@ -213,8 +213,8 @@ const struct brw_tracked_state brw_recalculate_urb_fence = {
.dirty = {
.mesa = 0,
.brw = BRW_NEW_CURBE_OFFSETS,
.cache = CACHE_NEW_SF_PROG |
CACHE_NEW_VS_PROG,
.cache = BRW_NEW_SF_PROG_DATA |
BRW_NEW_VS_PROG_DATA,
},
.emit = recalculate_urb_fence
};

4
src/mesa/drivers/dri/i965/brw_vs_state.c
View file

@ -47,7 +47,7 @@ brw_upload_vs_unit(struct brw_context *brw)
sizeof(*vs), 32, &stage_state->state_offset);
memset(vs, 0, sizeof(*vs));
/* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_VS_PROG */
/* BRW_NEW_PROGRAM_CACHE | BRW_NEW_VS_PROG_DATA */
vs->thread0.grf_reg_count =
ALIGN(brw->vs.prog_data->base.total_grf, 16) / 16 - 1;
vs->thread0.kernel_start_pointer =
@ -193,7 +193,7 @@ const struct brw_tracked_state brw_vs_unit = {
BRW_NEW_SAMPLER_STATE_TABLE |
BRW_NEW_URB_FENCE |
BRW_NEW_VERTEX_PROGRAM,
.cache = CACHE_NEW_VS_PROG,
.cache = BRW_NEW_VS_PROG_DATA,
},
.emit = brw_upload_vs_unit,
};

14
src/mesa/drivers/dri/i965/brw_vs_surface_state.c
View file

@ -72,7 +72,7 @@ brw_upload_pull_constants(struct brw_context *brw,
*/
_mesa_load_state_parameters(&brw->ctx, prog->Parameters);
/* CACHE_NEW_*_PROG | _NEW_PROGRAM_CONSTANTS */
/* BRW_NEW_*_PROG_DATA | _NEW_PROGRAM_CONSTANTS */
uint32_t size = prog_data->nr_pull_params * 4;
drm_intel_bo *const_bo = NULL;
uint32_t const_offset;
@ -117,7 +117,7 @@ brw_upload_vs_pull_constants(struct brw_context *brw)
struct brw_vertex_program *vp =
(struct brw_vertex_program *) brw->vertex_program;
/* CACHE_NEW_VS_PROG */
/* BRW_NEW_VS_PROG_DATA */
const struct brw_stage_prog_data *prog_data = &brw->vs.prog_data->base.base;
/* _NEW_PROGRAM_CONSTANTS */
@ -130,7 +130,7 @@ const struct brw_tracked_state brw_vs_pull_constants = {
.mesa = _NEW_PROGRAM_CONSTANTS,
.brw = BRW_NEW_BATCH |
BRW_NEW_VERTEX_PROGRAM,
.cache = CACHE_NEW_VS_PROG,
.cache = BRW_NEW_VS_PROG_DATA,
},
.emit = brw_upload_vs_pull_constants,
};
@ -146,7 +146,7 @@ brw_upload_vs_ubo_surfaces(struct brw_context *brw)
if (!prog)
return;
/* CACHE_NEW_VS_PROG */
/* BRW_NEW_VS_PROG_DATA */
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_VERTEX],
&brw->vs.base, &brw->vs.prog_data->base.base);
}
@ -156,7 +156,7 @@ const struct brw_tracked_state brw_vs_ubo_surfaces = {
.mesa = _NEW_PROGRAM,
.brw = BRW_NEW_BATCH |
BRW_NEW_UNIFORM_BUFFER,
.cache = CACHE_NEW_VS_PROG,
.cache = BRW_NEW_VS_PROG_DATA,
},
.emit = brw_upload_vs_ubo_surfaces,
};
@ -170,7 +170,7 @@ brw_upload_vs_abo_surfaces(struct brw_context *brw)
ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX];
if (prog) {
/* CACHE_NEW_VS_PROG */
/* BRW_NEW_VS_PROG_DATA */
brw_upload_abo_surfaces(brw, prog, &brw->vs.base,
&brw->vs.prog_data->base.base);
}
@ -181,7 +181,7 @@ const struct brw_tracked_state brw_vs_abo_surfaces = {
.mesa = _NEW_PROGRAM,
.brw = BRW_NEW_ATOMIC_BUFFER |
BRW_NEW_BATCH,
.cache = CACHE_NEW_VS_PROG,
.cache = BRW_NEW_VS_PROG_DATA,
},
.emit = brw_upload_vs_abo_surfaces,
};

6
src/mesa/drivers/dri/i965/brw_wm_state.c
View file

@ -77,7 +77,7 @@ brw_upload_wm_unit(struct brw_context *brw)
struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_FRAGMENT_PROGRAM */
const struct gl_fragment_program *fp = brw->fragment_program;
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
struct brw_wm_unit_state *wm;
@ -94,7 +94,7 @@ brw_upload_wm_unit(struct brw_context *brw)
prog_data->dispatch_grf_start_reg_16);
}
/* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_WM_PROG */
/* BRW_NEW_PROGRAM_CACHE | BRW_NEW_FS_PROG_DATA */
wm->thread0.grf_reg_count = prog_data->reg_blocks;
wm->wm9.grf_reg_count_2 = prog_data->reg_blocks_16;
@ -258,7 +258,7 @@ const struct brw_tracked_state brw_wm_unit = {
BRW_NEW_PROGRAM_CACHE |
BRW_NEW_SAMPLER_STATE_TABLE |
BRW_NEW_STATS_WM,
.cache = CACHE_NEW_WM_PROG,
.cache = BRW_NEW_FS_PROG_DATA,
},
.emit = brw_upload_wm_unit,
};

12
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View file

@ -483,7 +483,7 @@ brw_upload_wm_pull_constants(struct brw_context *brw)
/* BRW_NEW_FRAGMENT_PROGRAM */
struct brw_fragment_program *fp =
(struct brw_fragment_program *) brw->fragment_program;
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
struct brw_stage_prog_data *prog_data = &brw->wm.prog_data->base;
/* _NEW_PROGRAM_CONSTANTS */
@ -496,7 +496,7 @@ const struct brw_tracked_state brw_wm_pull_constants = {
.mesa = _NEW_PROGRAM_CONSTANTS,
.brw = BRW_NEW_BATCH |
BRW_NEW_FRAGMENT_PROGRAM,
.cache = CACHE_NEW_WM_PROG,
.cache = BRW_NEW_FS_PROG_DATA,
},
.emit = brw_upload_wm_pull_constants,
};
@ -883,7 +883,7 @@ brw_upload_wm_ubo_surfaces(struct brw_context *brw)
if (!prog)
return;
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
&brw->wm.base, &brw->wm.prog_data->base);
}
@ -893,7 +893,7 @@ const struct brw_tracked_state brw_wm_ubo_surfaces = {
.mesa = _NEW_PROGRAM,
.brw = BRW_NEW_BATCH |
BRW_NEW_UNIFORM_BUFFER,
.cache = CACHE_NEW_WM_PROG,
.cache = BRW_NEW_FS_PROG_DATA,
},
.emit = brw_upload_wm_ubo_surfaces,
};
@ -933,7 +933,7 @@ brw_upload_wm_abo_surfaces(struct brw_context *brw)
struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;
if (prog) {
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
brw_upload_abo_surfaces(brw, prog, &brw->wm.base,
&brw->wm.prog_data->base);
}
@ -944,7 +944,7 @@ const struct brw_tracked_state brw_wm_abo_surfaces = {
.mesa = _NEW_PROGRAM,
.brw = BRW_NEW_ATOMIC_BUFFER |
BRW_NEW_BATCH,
.cache = CACHE_NEW_WM_PROG,
.cache = BRW_NEW_FS_PROG_DATA,
},
.emit = brw_upload_wm_abo_surfaces,
};

6
src/mesa/drivers/dri/i965/gen6_clip_state.c
View file

@ -43,7 +43,7 @@ upload_clip_state(struct brw_context *brw)
/* _NEW_BUFFERS */
struct gl_framebuffer *fb = ctx->DrawBuffer;
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
if (brw->wm.prog_data->barycentric_interp_modes &
BRW_WM_NONPERSPECTIVE_BARYCENTRIC_BITS) {
dw2 |= GEN6_CLIP_NON_PERSPECTIVE_BARYCENTRIC_ENABLE;
@ -189,7 +189,7 @@ const struct brw_tracked_state gen6_clip_state = {
.brw = BRW_NEW_CONTEXT |
BRW_NEW_META_IN_PROGRESS |
BRW_NEW_RASTERIZER_DISCARD,
.cache = CACHE_NEW_WM_PROG
.cache = BRW_NEW_FS_PROG_DATA
},
.emit = upload_clip_state,
};
@ -203,7 +203,7 @@ const struct brw_tracked_state gen7_clip_state = {
.brw = BRW_NEW_CONTEXT |
BRW_NEW_META_IN_PROGRESS |
BRW_NEW_RASTERIZER_DISCARD,
.cache = CACHE_NEW_WM_PROG
.cache = BRW_NEW_FS_PROG_DATA
},
.emit = upload_clip_state,
};

10
src/mesa/drivers/dri/i965/gen6_gs_state.c
View file

@ -40,7 +40,7 @@ gen6_upload_gs_push_constants(struct brw_context *brw)
(struct brw_geometry_program *) brw->geometry_program;
if (gp) {
/* CACHE_NEW_GS_PROG */
/* BRW_NEW_GS_PROG_DATA */
struct brw_stage_prog_data *prog_data = &brw->gs.prog_data->base.base;
gen6_upload_push_constants(brw, &gp->program.Base, prog_data,
@ -58,7 +58,7 @@ const struct brw_tracked_state gen6_gs_push_constants = {
.brw = BRW_NEW_BATCH |
BRW_NEW_GEOMETRY_PROGRAM |
BRW_NEW_PUSH_CONSTANT_ALLOCATION,
.cache = CACHE_NEW_GS_PROG,
.cache = BRW_NEW_GS_PROG_DATA,
},
.emit = gen6_upload_gs_push_constants,
};
@ -90,7 +90,7 @@ upload_gs_state(struct brw_context *brw)
{
/* BRW_NEW_GEOMETRY_PROGRAM */
bool active = brw->geometry_program;
/* CACHE_NEW_GS_PROG */
/* BRW_NEW_GS_PROG_DATA */
const struct brw_vec4_prog_data *prog_data = &brw->gs.prog_data->base;
const struct brw_stage_state *stage_state = &brw->gs.base;
@ -202,8 +202,8 @@ const struct brw_tracked_state gen6_gs_state = {
BRW_NEW_CONTEXT |
BRW_NEW_GEOMETRY_PROGRAM |
BRW_NEW_PUSH_CONSTANT_ALLOCATION,
.cache = CACHE_NEW_FF_GS_PROG |
CACHE_NEW_GS_PROG,
.cache = BRW_NEW_FF_GS_PROG_DATA |
BRW_NEW_GS_PROG_DATA,
},
.emit = upload_gs_state,
};

8
src/mesa/drivers/dri/i965/gen6_sf_state.c
View file

@ -190,7 +190,7 @@ calculate_attr_overrides(const struct brw_context *brw,
enum glsl_interp_qualifier interp_qualifier =
brw->fragment_program->InterpQualifier[attr];
bool is_gl_Color = attr == VARYING_SLOT_COL0 || attr == VARYING_SLOT_COL1;
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
int input_index = brw->wm.prog_data->urb_setup[attr];
if (input_index < 0)
@ -259,7 +259,7 @@ static void
upload_sf_state(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
uint32_t num_outputs = brw->wm.prog_data->num_varying_inputs;
uint32_t dw1, dw2, dw3, dw4;
uint32_t point_sprite_enables;
@ -405,7 +405,7 @@ upload_sf_state(struct brw_context *brw)
}
/* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | CACHE_NEW_WM_PROG
* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
*/
uint32_t urb_entry_read_length;
calculate_attr_overrides(brw, attr_overrides, &point_sprite_enables,
@ -447,7 +447,7 @@ const struct brw_tracked_state gen6_sf_state = {
BRW_NEW_GEOMETRY_PROGRAM |
BRW_NEW_PRIMITIVE |
BRW_NEW_VUE_MAP_GEOM_OUT,
.cache = CACHE_NEW_WM_PROG
.cache = BRW_NEW_FS_PROG_DATA
},
.emit = upload_sf_state,
};

8
src/mesa/drivers/dri/i965/gen6_urb.c
View file

@ -54,7 +54,7 @@ gen6_upload_urb( struct brw_context *brw )
bool gs_present = brw->ff_gs.prog_active || brw->geometry_program;
/* CACHE_NEW_VS_PROG */
/* BRW_NEW_VS_PROG_DATA */
unsigned vs_size = MAX2(brw->vs.prog_data->base.urb_entry_size, 1);
/* Whe using GS to do transform feedback only we use the same VUE layout for
@ -129,9 +129,9 @@ const struct brw_tracked_state gen6_urb = {
.mesa = 0,
.brw = BRW_NEW_CONTEXT |
BRW_NEW_GEOMETRY_PROGRAM,
.cache = CACHE_NEW_GS_PROG |
CACHE_NEW_VS_PROG |
CACHE_NEW_FF_GS_PROG,
.cache = BRW_NEW_GS_PROG_DATA |
BRW_NEW_VS_PROG_DATA |
BRW_NEW_FF_GS_PROG_DATA,
},
.emit = gen6_upload_urb,
};

6
src/mesa/drivers/dri/i965/gen6_vs_state.c
View file

@ -130,7 +130,7 @@ gen6_upload_vs_push_constants(struct brw_context *brw)
/* _BRW_NEW_VERTEX_PROGRAM */
const struct brw_vertex_program *vp =
brw_vertex_program_const(brw->vertex_program);
/* CACHE_NEW_VS_PROG */
/* BRW_NEW_VS_PROG_DATA */
const struct brw_stage_prog_data *prog_data = &brw->vs.prog_data->base.base;
gen6_upload_push_constants(brw, &vp->program.Base, prog_data,
@ -152,7 +152,7 @@ const struct brw_tracked_state gen6_vs_push_constants = {
.brw = BRW_NEW_BATCH |
BRW_NEW_PUSH_CONSTANT_ALLOCATION |
BRW_NEW_VERTEX_PROGRAM,
.cache = CACHE_NEW_VS_PROG,
.cache = BRW_NEW_VS_PROG_DATA,
},
.emit = gen6_upload_vs_push_constants,
};
@ -266,7 +266,7 @@ const struct brw_tracked_state gen6_vs_state = {
BRW_NEW_CONTEXT |
BRW_NEW_PUSH_CONSTANT_ALLOCATION |
BRW_NEW_VERTEX_PROGRAM,
.cache = CACHE_NEW_VS_PROG
.cache = BRW_NEW_VS_PROG_DATA
},
.emit = upload_vs_state,
};

10
src/mesa/drivers/dri/i965/gen6_wm_state.c
View file

@ -42,7 +42,7 @@ gen6_upload_wm_push_constants(struct brw_context *brw)
/* BRW_NEW_FRAGMENT_PROGRAM */
const struct brw_fragment_program *fp =
brw_fragment_program_const(brw->fragment_program);
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
gen6_upload_push_constants(brw, &fp->program.Base, &prog_data->base,
@ -60,7 +60,7 @@ const struct brw_tracked_state gen6_wm_push_constants = {
.brw = BRW_NEW_BATCH |
BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_PUSH_CONSTANT_ALLOCATION,
.cache = CACHE_NEW_WM_PROG,
.cache = BRW_NEW_FS_PROG_DATA,
},
.emit = gen6_upload_wm_push_constants,
};
@ -72,7 +72,7 @@ upload_wm_state(struct brw_context *brw)
/* BRW_NEW_FRAGMENT_PROGRAM */
const struct brw_fragment_program *fp =
brw_fragment_program_const(brw->fragment_program);
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
uint32_t dw2, dw4, dw5, dw6, ksp0, ksp2;
@ -164,7 +164,7 @@ upload_wm_state(struct brw_context *brw)
ksp0 = brw->wm.base.prog_offset;
}
/* CACHE_NEW_WM_PROG | _NEW_COLOR */
/* BRW_NEW_FS_PROG_DATA | _NEW_COLOR */
if (prog_data->dual_src_blend &&
(ctx->Color.BlendEnabled & 1) &&
ctx->Color.Blend[0]._UsesDualSrc) {
@ -306,7 +306,7 @@ const struct brw_tracked_state gen6_wm_state = {
.brw = BRW_NEW_BATCH |
BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_PUSH_CONSTANT_ALLOCATION,
.cache = CACHE_NEW_WM_PROG
.cache = BRW_NEW_FS_PROG_DATA
},
.emit = upload_wm_state,
};

4
src/mesa/drivers/dri/i965/gen7_gs_state.c
View file

@ -34,7 +34,7 @@ upload_gs_state(struct brw_context *brw)
HSW_GS_MAX_THREADS_SHIFT : GEN6_GS_MAX_THREADS_SHIFT;
/* BRW_NEW_GEOMETRY_PROGRAM */
bool active = brw->geometry_program;
/* CACHE_NEW_GS_PROG */
/* BRW_NEW_GS_PROG_DATA */
const struct brw_vec4_prog_data *prog_data = &brw->gs.prog_data->base;
/**
@ -157,7 +157,7 @@ const struct brw_tracked_state gen7_gs_state = {
.brw = BRW_NEW_BATCH |
BRW_NEW_CONTEXT |
BRW_NEW_GEOMETRY_PROGRAM,
.cache = CACHE_NEW_GS_PROG
.cache = BRW_NEW_GS_PROG_DATA
},
.emit = upload_gs_state,
};

6
src/mesa/drivers/dri/i965/gen7_sf_state.c
View file

@ -33,7 +33,7 @@ static void
upload_sbe_state(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
uint32_t num_outputs = brw->wm.prog_data->num_varying_inputs;
uint32_t dw1;
uint32_t point_sprite_enables;
@ -61,7 +61,7 @@ upload_sbe_state(struct brw_context *brw)
dw1 |= point_sprite_origin;
/* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM
* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | CACHE_NEW_WM_PROG
* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
*/
uint32_t urb_entry_read_length;
calculate_attr_overrides(brw, attr_overrides, &point_sprite_enables,
@ -96,7 +96,7 @@ const struct brw_tracked_state gen7_sbe_state = {
BRW_NEW_GEOMETRY_PROGRAM |
BRW_NEW_PRIMITIVE |
BRW_NEW_VUE_MAP_GEOM_OUT,
.cache = CACHE_NEW_WM_PROG
.cache = BRW_NEW_FS_PROG_DATA
},
.emit = upload_sbe_state,
};

8
src/mesa/drivers/dri/i965/gen7_urb.c
View file

@ -142,10 +142,10 @@ gen7_upload_urb(struct brw_context *brw)
const int push_size_kB =
(brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16;
/* CACHE_NEW_VS_PROG */
/* BRW_NEW_VS_PROG_DATA */
unsigned vs_size = MAX2(brw->vs.prog_data->base.urb_entry_size, 1);
unsigned vs_entry_size_bytes = vs_size * 64;
/* BRW_NEW_GEOMETRY_PROGRAM, CACHE_NEW_GS_PROG */
/* BRW_NEW_GEOMETRY_PROGRAM, BRW_NEW_GS_PROG_DATA */
bool gs_present = brw->geometry_program;
unsigned gs_size = gs_present ? brw->gs.prog_data->base.urb_entry_size : 1;
unsigned gs_entry_size_bytes = gs_size * 64;
@ -316,8 +316,8 @@ const struct brw_tracked_state gen7_urb = {
.mesa = 0,
.brw = BRW_NEW_CONTEXT |
BRW_NEW_GEOMETRY_PROGRAM,
.cache = CACHE_NEW_VS_PROG |
CACHE_NEW_GS_PROG,
.cache = BRW_NEW_VS_PROG_DATA |
BRW_NEW_GS_PROG_DATA,
},
.emit = gen7_upload_urb,
};

2
src/mesa/drivers/dri/i965/gen7_vs_state.c
View file

@ -115,7 +115,7 @@ const struct brw_tracked_state gen7_vs_state = {
.brw = BRW_NEW_BATCH |
BRW_NEW_CONTEXT |
BRW_NEW_VERTEX_PROGRAM,
.cache = CACHE_NEW_VS_PROG
.cache = BRW_NEW_VS_PROG_DATA
},
.emit = upload_vs_state,
};

12
src/mesa/drivers/dri/i965/gen7_wm_state.c
View file

@ -39,7 +39,7 @@ upload_wm_state(struct brw_context *brw)
/* BRW_NEW_FRAGMENT_PROGRAM */
const struct brw_fragment_program *fp =
brw_fragment_program_const(brw->fragment_program);
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
bool writes_depth = false;
uint32_t dw1, dw2;
@ -133,7 +133,7 @@ const struct brw_tracked_state gen7_wm_state = {
_NEW_POLYGON,
.brw = BRW_NEW_BATCH |
BRW_NEW_FRAGMENT_PROGRAM,
.cache = CACHE_NEW_WM_PROG,
.cache = BRW_NEW_FS_PROG_DATA,
},
.emit = upload_wm_state,
};
@ -146,7 +146,7 @@ upload_ps_state(struct brw_context *brw)
const int max_threads_shift = brw->is_haswell ?
HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
dw2 = dw4 = dw5 = ksp2 = 0;
@ -203,7 +203,7 @@ upload_ps_state(struct brw_context *brw)
else
dw4 |= GEN7_PS_POSOFFSET_NONE;
/* CACHE_NEW_WM_PROG | _NEW_COLOR
/* BRW_NEW_FS_PROG_DATA | _NEW_COLOR
*
* The hardware wedges if you have this bit set but don't turn on any dual
* source blend factors.
@ -214,7 +214,7 @@ upload_ps_state(struct brw_context *brw)
dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
}
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
if (prog_data->num_varying_inputs != 0)
dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
@ -277,7 +277,7 @@ const struct brw_tracked_state gen7_ps_state = {
_NEW_MULTISAMPLE,
.brw = BRW_NEW_BATCH |
BRW_NEW_FRAGMENT_PROGRAM,
.cache = CACHE_NEW_WM_PROG
.cache = BRW_NEW_FS_PROG_DATA
},
.emit = upload_ps_state,
};

6
src/mesa/drivers/dri/i965/gen8_depth_state.c
View file

@ -286,8 +286,8 @@ pma_fix_enable(const struct brw_context *brw)
(fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) &&
fp->FragDepthLayout != FRAG_DEPTH_LAYOUT_UNCHANGED;
/* CACHE_NEW_WM_PROG: 3DSTATE_PS_EXTRA::PixelShaderKillsPixels
* CACHE_NEW_WM_PROG: 3DSTATE_PS_EXTRA::oMask Present to RenderTarget
/* BRW_NEW_FS_PROG_DATA: 3DSTATE_PS_EXTRA::PixelShaderKillsPixels
* BRW_NEW_FS_PROG_DATA: 3DSTATE_PS_EXTRA::oMask Present to RenderTarget
* _NEW_MULTISAMPLE: 3DSTATE_PS_BLEND::AlphaToCoverageEnable
* _NEW_COLOR: 3DSTATE_PS_BLEND::AlphaTestEnable
*
@ -373,7 +373,7 @@ const struct brw_tracked_state gen8_pma_fix = {
_NEW_MULTISAMPLE |
_NEW_STENCIL,
.brw = BRW_NEW_FRAGMENT_PROGRAM,
.cache = CACHE_NEW_WM_PROG,
.cache = BRW_NEW_FS_PROG_DATA,
},
.emit = gen8_emit_pma_stall_workaround
};

2
src/mesa/drivers/dri/i965/gen8_draw_upload.c
View file

@ -235,7 +235,7 @@ const struct brw_tracked_state gen8_vertices = {
.mesa = _NEW_POLYGON,
.brw = BRW_NEW_BATCH |
BRW_NEW_VERTICES,
.cache = CACHE_NEW_VS_PROG,
.cache = BRW_NEW_VS_PROG_DATA,
},
.emit = gen8_emit_vertices,
};

4
src/mesa/drivers/dri/i965/gen8_gs_state.c
View file

@ -33,7 +33,7 @@ gen8_upload_gs_state(struct brw_context *brw)
const struct brw_stage_state *stage_state = &brw->gs.base;
/* BRW_NEW_GEOMETRY_PROGRAM */
bool active = brw->geometry_program;
/* CACHE_NEW_GS_PROG */
/* BRW_NEW_GS_PROG_DATA */
const struct brw_vec4_prog_data *prog_data = &brw->gs.prog_data->base;
if (active) {
@ -123,7 +123,7 @@ const struct brw_tracked_state gen8_gs_state = {
.brw = BRW_NEW_BATCH |
BRW_NEW_CONTEXT |
BRW_NEW_GEOMETRY_PROGRAM,
.cache = CACHE_NEW_GS_PROG
.cache = BRW_NEW_GS_PROG_DATA
},
.emit = gen8_upload_gs_state,
};

14
src/mesa/drivers/dri/i965/gen8_ps_state.c
View file

@ -34,7 +34,7 @@ upload_ps_extra(struct brw_context *brw)
/* BRW_NEW_FRAGMENT_PROGRAM */
const struct brw_fragment_program *fp =
brw_fragment_program_const(brw->fragment_program);
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
uint32_t dw1 = 0;
@ -90,7 +90,7 @@ const struct brw_tracked_state gen8_ps_extra = {
.brw = BRW_NEW_CONTEXT |
BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_NUM_SAMPLES,
.cache = CACHE_NEW_WM_PROG,
.cache = BRW_NEW_FS_PROG_DATA,
},
.emit = upload_ps_extra,
};
@ -114,7 +114,7 @@ upload_wm_state(struct brw_context *brw)
if (ctx->Polygon.StippleFlag)
dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
@ -129,7 +129,7 @@ const struct brw_tracked_state gen8_wm_state = {
.mesa = _NEW_LINE |
_NEW_POLYGON,
.brw = BRW_NEW_CONTEXT,
.cache = CACHE_NEW_WM_PROG,
.cache = BRW_NEW_FS_PROG_DATA,
},
.emit = upload_wm_state,
};
@ -140,7 +140,7 @@ upload_ps_state(struct brw_context *brw)
struct gl_context *ctx = &brw->ctx;
uint32_t dw3 = 0, dw6 = 0, dw7 = 0, ksp0, ksp2 = 0;
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
/* Initialize the execution mask with VMask. Otherwise, derivatives are
@ -152,7 +152,7 @@ upload_ps_state(struct brw_context *brw)
dw3 |=
(ALIGN(brw->wm.base.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
dw3 |=
((prog_data->base.binding_table.size_bytes / 4) <<
GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
@ -253,7 +253,7 @@ const struct brw_tracked_state gen8_ps_state = {
.mesa = _NEW_MULTISAMPLE,
.brw = BRW_NEW_BATCH |
BRW_NEW_FRAGMENT_PROGRAM,
.cache = CACHE_NEW_WM_PROG
.cache = BRW_NEW_FS_PROG_DATA
},
.emit = upload_ps_state,
};

6
src/mesa/drivers/dri/i965/gen8_sf_state.c
View file

@ -33,7 +33,7 @@ static void
upload_sbe(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
/* CACHE_NEW_WM_PROG */
/* BRW_NEW_FS_PROG_DATA */
uint32_t num_outputs = brw->wm.prog_data->num_varying_inputs;
uint16_t attr_overrides[VARYING_SLOT_MAX];
uint32_t urb_entry_read_length;
@ -61,7 +61,7 @@ upload_sbe(struct brw_context *brw)
dw1 |= GEN6_SF_POINT_SPRITE_UPPERLEFT;
/* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | CACHE_NEW_WM_PROG
* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
*/
calculate_attr_overrides(brw, attr_overrides,
&point_sprite_enables,
@ -134,7 +134,7 @@ const struct brw_tracked_state gen8_sbe_state = {
.brw = BRW_NEW_CONTEXT |
BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_VUE_MAP_GEOM_OUT,
.cache = CACHE_NEW_WM_PROG,
.cache = BRW_NEW_FS_PROG_DATA,
},
.emit = upload_sbe,
};

4
src/mesa/drivers/dri/i965/gen8_vs_state.c
View file

@ -36,7 +36,7 @@ upload_vs_state(struct brw_context *brw)
const struct brw_stage_state *stage_state = &brw->vs.base;
uint32_t floating_point_mode = 0;
/* CACHE_NEW_VS_PROG */
/* BRW_NEW_VS_PROG_DATA */
const struct brw_vec4_prog_data *prog_data = &brw->vs.prog_data->base;
/* Use ALT floating point mode for ARB vertex programs, because they
@ -85,7 +85,7 @@ const struct brw_tracked_state gen8_vs_state = {
.brw = BRW_NEW_BATCH |
BRW_NEW_CONTEXT |
BRW_NEW_VERTEX_PROGRAM,
.cache = CACHE_NEW_VS_PROG
.cache = BRW_NEW_VS_PROG_DATA
},
.emit = upload_vs_state,
};