mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-05 09:38:07 +02:00
radv: Add occlusion query shader.
Adds a shader for writing occlusion query results to a buffer, as the CP packet isn't support on SI or secondary buffers, and doesn't handle the availability bit (or partial results) nor truncation to 32-bit. Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Bas Nieuwenhuizen
parent
50b987c0f0
commit
ce0c8cf941
4 changed files with 435 additions and 0 deletions
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@ -324,6 +324,10 @@ radv_device_init_meta(struct radv_device *device)
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if (result != VK_SUCCESS)
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goto fail_buffer;
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result = radv_device_init_meta_query_state(device);
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if (result != VK_SUCCESS)
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goto fail_query;
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result = radv_device_init_meta_fast_clear_flush_state(device);
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if (result != VK_SUCCESS)
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goto fail_fast_clear;
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@ -337,6 +341,8 @@ fail_resolve_compute:
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radv_device_finish_meta_fast_clear_flush_state(device);
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fail_fast_clear:
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radv_device_finish_meta_buffer_state(device);
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fail_query:
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radv_device_finish_meta_query_state(device);
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fail_buffer:
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radv_device_finish_meta_depth_decomp_state(device);
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fail_depth_decomp:
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@ -363,6 +369,7 @@ radv_device_finish_meta(struct radv_device *device)
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radv_device_finish_meta_blit2d_state(device);
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radv_device_finish_meta_bufimage_state(device);
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radv_device_finish_meta_depth_decomp_state(device);
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radv_device_finish_meta_query_state(device);
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radv_device_finish_meta_buffer_state(device);
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radv_device_finish_meta_fast_clear_flush_state(device);
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radv_device_finish_meta_resolve_compute_state(device);
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@ -85,6 +85,9 @@ void radv_device_finish_meta_blit2d_state(struct radv_device *device);
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VkResult radv_device_init_meta_buffer_state(struct radv_device *device);
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void radv_device_finish_meta_buffer_state(struct radv_device *device);
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VkResult radv_device_init_meta_query_state(struct radv_device *device);
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void radv_device_finish_meta_query_state(struct radv_device *device);
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VkResult radv_device_init_meta_resolve_compute_state(struct radv_device *device);
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void radv_device_finish_meta_resolve_compute_state(struct radv_device *device);
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void radv_meta_save(struct radv_meta_saved_state *state,
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@ -438,6 +438,12 @@ struct radv_meta_state {
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VkPipeline fill_pipeline;
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VkPipeline copy_pipeline;
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} buffer;
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struct {
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VkDescriptorSetLayout occlusion_query_ds_layout;
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VkPipelineLayout occlusion_query_p_layout;
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VkPipeline occlusion_query_pipeline;
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} query;
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};
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/* queue types */
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@ -29,6 +29,8 @@
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#include <unistd.h>
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#include <fcntl.h>
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#include "nir/nir_builder.h"
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#include "radv_meta.h"
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#include "radv_private.h"
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#include "radv_cs.h"
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#include "sid.h"
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@ -49,6 +51,423 @@ static unsigned get_max_db(struct radv_device *device)
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return num_db;
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}
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static void radv_break_on_count(nir_builder *b, nir_variable *var, int count)
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{
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nir_ssa_def *counter = nir_load_var(b, var);
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nir_if *if_stmt = nir_if_create(b->shader);
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if_stmt->condition = nir_src_for_ssa(nir_uge(b, counter, nir_imm_int(b, count)));
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nir_cf_node_insert(b->cursor, &if_stmt->cf_node);
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b->cursor = nir_after_cf_list(&if_stmt->then_list);
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nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_break);
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nir_builder_instr_insert(b, &instr->instr);
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b->cursor = nir_after_cf_node(&if_stmt->cf_node);
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counter = nir_iadd(b, counter, nir_imm_int(b, 1));
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nir_store_var(b, var, counter, 0x1);
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}
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static struct nir_ssa_def *
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radv_load_push_int(nir_builder *b, unsigned offset, const char *name)
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{
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nir_intrinsic_instr *flags = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
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flags->src[0] = nir_src_for_ssa(nir_imm_int(b, offset));
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flags->num_components = 1;
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nir_ssa_dest_init(&flags->instr, &flags->dest, 1, 32, name);
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nir_builder_instr_insert(b, &flags->instr);
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return &flags->dest.ssa;
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}
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static nir_shader *
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build_occlusion_query_shader(struct radv_device *device) {
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/* the shader this builds is roughly
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*
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* push constants {
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* uint32_t flags;
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* uint32_t dst_stride;
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* };
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*
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* uint32_t src_stride = 16 * db_count;
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*
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* location(binding = 0) buffer dst_buf;
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* location(binding = 1) buffer src_buf;
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*
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* void main() {
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* uint64_t result = 0;
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* uint64_t src_offset = src_stride * global_id.x;
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* uint64_t dst_offset = dst_stride * global_id.x;
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* bool available = true;
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* for (int i = 0; i < db_count; ++i) {
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* uint64_t start = src_buf[src_offset + 16 * i];
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* uint64_t end = src_buf[src_offset + 16 * i + 8];
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* if ((start & (1ull << 63)) && (end & (1ull << 63)))
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* result += end - start;
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* else
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* available = false;
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* }
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* uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
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* if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {
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* if (flags & VK_QUERY_RESULT_64_BIT)
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* dst_buf[dst_offset] = result;
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* else
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* dst_buf[dst_offset] = (uint32_t)result.
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* }
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* if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
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* dst_buf[dst_offset + elem_size] = available;
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* }
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* }
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*/
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nir_builder b;
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nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
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b.shader->info->name = ralloc_strdup(b.shader, "occlusion_query");
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b.shader->info->cs.local_size[0] = 64;
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b.shader->info->cs.local_size[1] = 1;
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b.shader->info->cs.local_size[2] = 1;
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nir_variable *result = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "result");
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nir_variable *outer_counter = nir_local_variable_create(b.impl, glsl_int_type(), "outer_counter");
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nir_variable *start = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "start");
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nir_variable *end = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "end");
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nir_variable *available = nir_local_variable_create(b.impl, glsl_int_type(), "available");
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unsigned db_count = get_max_db(device);
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nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
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nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
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nir_intrinsic_vulkan_resource_index);
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dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
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nir_intrinsic_set_desc_set(dst_buf, 0);
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nir_intrinsic_set_binding(dst_buf, 0);
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nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, 1, 32, NULL);
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nir_builder_instr_insert(&b, &dst_buf->instr);
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nir_intrinsic_instr *src_buf = nir_intrinsic_instr_create(b.shader,
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nir_intrinsic_vulkan_resource_index);
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src_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
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nir_intrinsic_set_desc_set(src_buf, 0);
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nir_intrinsic_set_binding(src_buf, 1);
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nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, 1, 32, NULL);
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nir_builder_instr_insert(&b, &src_buf->instr);
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nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
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nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
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nir_ssa_def *block_size = nir_imm_ivec4(&b,
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b.shader->info->cs.local_size[0],
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b.shader->info->cs.local_size[1],
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b.shader->info->cs.local_size[2], 0);
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nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
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global_id = nir_channel(&b, global_id, 0); // We only care about x here.
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nir_ssa_def *input_stride = nir_imm_int(&b, db_count * 16);
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nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);
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nir_ssa_def *output_stride = radv_load_push_int(&b, 4, "output_stride");
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nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);
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nir_store_var(&b, result, nir_imm_int64(&b, 0), 0x1);
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nir_store_var(&b, outer_counter, nir_imm_int(&b, 0), 0x1);
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nir_store_var(&b, available, nir_imm_int(&b, 1), 0x1);
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nir_loop *outer_loop = nir_loop_create(b.shader);
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nir_builder_cf_insert(&b, &outer_loop->cf_node);
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b.cursor = nir_after_cf_list(&outer_loop->body);
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nir_ssa_def *current_outer_count = nir_load_var(&b, outer_counter);
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radv_break_on_count(&b, outer_counter, db_count);
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nir_ssa_def *load_offset = nir_imul(&b, current_outer_count, nir_imm_int(&b, 16));
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load_offset = nir_iadd(&b, input_base, load_offset);
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nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
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load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
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load->src[1] = nir_src_for_ssa(load_offset);
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nir_ssa_dest_init(&load->instr, &load->dest, 2, 64, NULL);
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load->num_components = 2;
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nir_builder_instr_insert(&b, &load->instr);
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const unsigned swizzle0[] = {0,0,0,0};
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const unsigned swizzle1[] = {1,1,1,1};
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nir_store_var(&b, start, nir_swizzle(&b, &load->dest.ssa, swizzle0, 1, false), 0x1);
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nir_store_var(&b, end, nir_swizzle(&b, &load->dest.ssa, swizzle1, 1, false), 0x1);
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nir_ssa_def *start_done = nir_ilt(&b, nir_load_var(&b, start), nir_imm_int64(&b, 0));
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nir_ssa_def *end_done = nir_ilt(&b, nir_load_var(&b, end), nir_imm_int64(&b, 0));
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nir_if *update_if = nir_if_create(b.shader);
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update_if->condition = nir_src_for_ssa(nir_iand(&b, start_done, end_done));
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nir_cf_node_insert(b.cursor, &update_if->cf_node);
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b.cursor = nir_after_cf_list(&update_if->then_list);
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nir_store_var(&b, result,
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nir_iadd(&b, nir_load_var(&b, result),
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nir_isub(&b, nir_load_var(&b, end),
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nir_load_var(&b, start))), 0x1);
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b.cursor = nir_after_cf_list(&update_if->else_list);
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nir_store_var(&b, available, nir_imm_int(&b, 0), 0x1);
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b.cursor = nir_after_cf_node(&outer_loop->cf_node);
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/* Store the result if complete or if partial results have been requested. */
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nir_ssa_def *result_is_64bit = nir_iand(&b, flags,
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nir_imm_int(&b, VK_QUERY_RESULT_64_BIT));
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nir_ssa_def *result_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));
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nir_if *store_if = nir_if_create(b.shader);
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store_if->condition = nir_src_for_ssa(nir_ior(&b, nir_iand(&b, flags, nir_imm_int(&b, VK_QUERY_RESULT_PARTIAL_BIT)), nir_load_var(&b, available)));
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nir_cf_node_insert(b.cursor, &store_if->cf_node);
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b.cursor = nir_after_cf_list(&store_if->then_list);
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nir_if *store_64bit_if = nir_if_create(b.shader);
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store_64bit_if->condition = nir_src_for_ssa(result_is_64bit);
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nir_cf_node_insert(b.cursor, &store_64bit_if->cf_node);
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b.cursor = nir_after_cf_list(&store_64bit_if->then_list);
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nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
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store->src[0] = nir_src_for_ssa(nir_load_var(&b, result));
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store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
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store->src[2] = nir_src_for_ssa(output_base);
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nir_intrinsic_set_write_mask(store, 0x1);
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store->num_components = 1;
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nir_builder_instr_insert(&b, &store->instr);
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b.cursor = nir_after_cf_list(&store_64bit_if->else_list);
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store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
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store->src[0] = nir_src_for_ssa(nir_u2u32(&b, nir_load_var(&b, result)));
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store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
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store->src[2] = nir_src_for_ssa(output_base);
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nir_intrinsic_set_write_mask(store, 0x1);
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store->num_components = 1;
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nir_builder_instr_insert(&b, &store->instr);
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b.cursor = nir_after_cf_node(&store_if->cf_node);
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/* Store the availability bit if requested. */
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nir_if *availability_if = nir_if_create(b.shader);
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availability_if->condition = nir_src_for_ssa(nir_iand(&b, flags, nir_imm_int(&b, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)));
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nir_cf_node_insert(b.cursor, &availability_if->cf_node);
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b.cursor = nir_after_cf_list(&availability_if->then_list);
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store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
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store->src[0] = nir_src_for_ssa(nir_load_var(&b, available));
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store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
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store->src[2] = nir_src_for_ssa(nir_iadd(&b, result_size, output_base));
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nir_intrinsic_set_write_mask(store, 0x1);
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store->num_components = 1;
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nir_builder_instr_insert(&b, &store->instr);
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return b.shader;
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}
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VkResult radv_device_init_meta_query_state(struct radv_device *device)
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{
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VkResult result;
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struct radv_shader_module occlusion_cs = { .nir = NULL };
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zero(device->meta_state.query);
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occlusion_cs.nir = build_occlusion_query_shader(device);
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VkDescriptorSetLayoutCreateInfo occlusion_ds_create_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.bindingCount = 2,
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.pBindings = (VkDescriptorSetLayoutBinding[]) {
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{
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.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL
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},
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{
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.binding = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL
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},
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}
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};
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result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
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&occlusion_ds_create_info,
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&device->meta_state.alloc,
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&device->meta_state.query.occlusion_query_ds_layout);
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if (result != VK_SUCCESS)
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goto fail;
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VkPipelineLayoutCreateInfo occlusion_pl_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 1,
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.pSetLayouts = &device->meta_state.query.occlusion_query_ds_layout,
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.pushConstantRangeCount = 1,
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.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 8},
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};
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result = radv_CreatePipelineLayout(radv_device_to_handle(device),
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&occlusion_pl_create_info,
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&device->meta_state.alloc,
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&device->meta_state.query.occlusion_query_p_layout);
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if (result != VK_SUCCESS)
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goto fail;
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VkPipelineShaderStageCreateInfo occlusion_pipeline_shader_stage = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = radv_shader_module_to_handle(&occlusion_cs),
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.pName = "main",
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.pSpecializationInfo = NULL,
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};
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VkComputePipelineCreateInfo occlusion_vk_pipeline_info = {
|
||||
.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
|
||||
.stage = occlusion_pipeline_shader_stage,
|
||||
.flags = 0,
|
||||
.layout = device->meta_state.query.occlusion_query_p_layout,
|
||||
};
|
||||
|
||||
result = radv_CreateComputePipelines(radv_device_to_handle(device),
|
||||
radv_pipeline_cache_to_handle(&device->meta_state.cache),
|
||||
1, &occlusion_vk_pipeline_info, NULL,
|
||||
&device->meta_state.query.occlusion_query_pipeline);
|
||||
if (result != VK_SUCCESS)
|
||||
goto fail;
|
||||
|
||||
return VK_SUCCESS;
|
||||
fail:
|
||||
radv_device_finish_meta_query_state(device);
|
||||
ralloc_free(occlusion_cs.nir);
|
||||
return result;
|
||||
}
|
||||
|
||||
void radv_device_finish_meta_query_state(struct radv_device *device)
|
||||
{
|
||||
if (device->meta_state.query.occlusion_query_pipeline)
|
||||
radv_DestroyPipeline(radv_device_to_handle(device),
|
||||
device->meta_state.query.occlusion_query_pipeline,
|
||||
&device->meta_state.alloc);
|
||||
|
||||
if (device->meta_state.query.occlusion_query_p_layout)
|
||||
radv_DestroyPipelineLayout(radv_device_to_handle(device),
|
||||
device->meta_state.query.occlusion_query_p_layout,
|
||||
&device->meta_state.alloc);
|
||||
|
||||
if (device->meta_state.query.occlusion_query_ds_layout)
|
||||
radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
|
||||
device->meta_state.query.occlusion_query_ds_layout,
|
||||
&device->meta_state.alloc);
|
||||
}
|
||||
|
||||
static void occlusion_query_shader(struct radv_cmd_buffer *cmd_buffer,
|
||||
struct radeon_winsys_bo *src_bo,
|
||||
struct radeon_winsys_bo *dst_bo,
|
||||
uint64_t src_offset, uint64_t dst_offset,
|
||||
uint32_t dst_stride, uint32_t count,
|
||||
uint32_t flags)
|
||||
{
|
||||
struct radv_device *device = cmd_buffer->device;
|
||||
struct radv_meta_saved_compute_state saved_state;
|
||||
unsigned stride = get_max_db(device) * 16;
|
||||
VkDescriptorSet ds;
|
||||
|
||||
radv_meta_save_compute(&saved_state, cmd_buffer, 4);
|
||||
|
||||
radv_temp_descriptor_set_create(device, cmd_buffer,
|
||||
device->meta_state.query.occlusion_query_ds_layout,
|
||||
&ds);
|
||||
|
||||
struct radv_buffer dst_buffer = {
|
||||
.bo = dst_bo,
|
||||
.offset = dst_offset,
|
||||
.size = dst_stride * count
|
||||
};
|
||||
|
||||
struct radv_buffer src_buffer = {
|
||||
.bo = src_bo,
|
||||
.offset = src_offset,
|
||||
.size = stride * count
|
||||
};
|
||||
|
||||
radv_UpdateDescriptorSets(radv_device_to_handle(device),
|
||||
2, /* writeCount */
|
||||
(VkWriteDescriptorSet[]) {
|
||||
{
|
||||
.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
||||
.dstSet = ds,
|
||||
.dstBinding = 0,
|
||||
.dstArrayElement = 0,
|
||||
.descriptorCount = 1,
|
||||
.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
|
||||
.pBufferInfo = &(VkDescriptorBufferInfo) {
|
||||
.buffer = radv_buffer_to_handle(&dst_buffer),
|
||||
.offset = 0,
|
||||
.range = dst_stride * count
|
||||
}
|
||||
},
|
||||
{
|
||||
.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
||||
.dstSet = ds,
|
||||
.dstBinding = 1,
|
||||
.dstArrayElement = 0,
|
||||
.descriptorCount = 1,
|
||||
.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
|
||||
.pBufferInfo = &(VkDescriptorBufferInfo) {
|
||||
.buffer = radv_buffer_to_handle(&src_buffer),
|
||||
.offset = 0,
|
||||
.range = stride * count
|
||||
}
|
||||
}
|
||||
}, 0, NULL);
|
||||
|
||||
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
|
||||
VK_PIPELINE_BIND_POINT_COMPUTE,
|
||||
device->meta_state.query.occlusion_query_pipeline);
|
||||
|
||||
radv_CmdBindDescriptorSets(radv_cmd_buffer_to_handle(cmd_buffer),
|
||||
VK_PIPELINE_BIND_POINT_COMPUTE,
|
||||
device->meta_state.query.occlusion_query_p_layout, 0, 1,
|
||||
&ds, 0, NULL);
|
||||
|
||||
struct {
|
||||
uint32_t flags;
|
||||
uint32_t dst_stride;
|
||||
} push_constants = {
|
||||
flags,
|
||||
dst_stride
|
||||
};
|
||||
|
||||
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
|
||||
device->meta_state.query.occlusion_query_p_layout,
|
||||
VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(push_constants),
|
||||
&push_constants);
|
||||
|
||||
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2 |
|
||||
RADV_CMD_FLAG_INV_VMEM_L1;
|
||||
|
||||
if (flags & VK_QUERY_RESULT_WAIT_BIT)
|
||||
cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER;
|
||||
|
||||
radv_unaligned_dispatch(cmd_buffer, count, 1, 1);
|
||||
|
||||
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2 |
|
||||
RADV_CMD_FLAG_INV_VMEM_L1 |
|
||||
RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
|
||||
|
||||
radv_temp_descriptor_set_destroy(device, ds);
|
||||
|
||||
radv_meta_restore_compute(&saved_state, cmd_buffer, 4);
|
||||
}
|
||||
|
||||
VkResult radv_CreateQueryPool(
|
||||
VkDevice _device,
|
||||
const VkQueryPoolCreateInfo* pCreateInfo,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue