fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-24 15:20:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

i965/msaa: Only do multisample rasterization if GL_MULTISAMPLE enabled.

Browse source 
From the GL 3.0 spec (p.116):

    "Multisample rasterization is enabled or disabled by calling
    Enable or Disable with the symbolic constant MULTISAMPLE."

Elsewhere in the spec, where multisample rasterization is described
(sections 3.4.3, 3.5.4, and 3.6.6), the following text is consistently
used:

    "If MULTISAMPLE is enabled, and the value of SAMPLE_BUFFERS is
    one, then..."

So, in other words, disabling GL_MULTISAMPLE should prevent
multisample rasterization from occurring, even if the draw framebuffer
is multisampled.  This patch implements that behaviour by setting the
WM and SF stage's "multisample rasterization mode" to
MSRAST_ON_PATTERN only when the draw framebuffer is multisampled *and*
GL_MULTISAMPLE is enabled.

Fixes piglit test spec/EXT_framebuffer_multisample/enable-flag.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Paul Berry 2012-06-16 11:32:04 -07:00
parent 3b0279a693
commit cde6544ad7
4 changed files with 32 additions and 18 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
src/mesa/drivers/dri/i965/gen6_sf_state.c
View file

@ -122,9 +122,9 @@ upload_sf_state(struct brw_context *brw)
int i;
/* _NEW_BUFFER */
bool render_to_fbo = _mesa_is_user_fbo(brw->intel.ctx.DrawBuffer);
bool multisampled = false;
bool multisampled_fbo = false;
if (ctx->DrawBuffer->_ColorDrawBuffers[0])
multisampled = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples > 0;
multisampled_fbo = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples > 0;
int attr = 0, input_index = 0;
int urb_entry_read_offset = 1;
@ -242,7 +242,8 @@ upload_sf_state(struct brw_context *brw)
dw3 |= GEN6_SF_LINE_AA_MODE_TRUE;
dw3 |= GEN6_SF_LINE_END_CAP_WIDTH_1_0;
}
if (multisampled)
/* _NEW_MULTISAMPLE */
if (multisampled_fbo && ctx->Multisample.Enabled)
dw3 |= GEN6_SF_MSRAST_ON_PATTERN;
/* _NEW_PROGRAM | _NEW_POINT */
@ -349,7 +350,8 @@ const struct brw_tracked_state gen6_sf_state = {
_NEW_LINE |
_NEW_SCISSOR |
_NEW_BUFFERS |
_NEW_POINT),
_NEW_POINT |
_NEW_MULTISAMPLE),
.brw = (BRW_NEW_CONTEXT |
BRW_NEW_FRAGMENT_PROGRAM),
.cache = CACHE_NEW_VS_PROG

15
src/mesa/drivers/dri/i965/gen6_wm_state.c
View file

@ -98,11 +98,11 @@ upload_wm_state(struct brw_context *brw)
const struct brw_fragment_program *fp =
brw_fragment_program_const(brw->fragment_program);
uint32_t dw2, dw4, dw5, dw6;
bool multisampled = false;
bool multisampled_fbo = false;
/* _NEW_BUFFERS */
if (ctx->DrawBuffer->_ColorDrawBuffers[0])
multisampled = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples > 0;
multisampled_fbo = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples > 0;
/* CACHE_NEW_WM_PROG */
if (brw->wm.prog_data->nr_params == 0) {
@ -197,8 +197,12 @@ upload_wm_state(struct brw_context *brw)
dw6 |= _mesa_bitcount_64(brw->fragment_program->Base.InputsRead) <<
GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
if (multisampled) {
dw6 |= GEN6_WM_MSRAST_ON_PATTERN;
if (multisampled_fbo) {
/* _NEW_MULTISAMPLE */
if (ctx->Multisample.Enabled)
dw6 |= GEN6_WM_MSRAST_ON_PATTERN;
else
dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
dw6 |= GEN6_WM_MSDISPMODE_PERPIXEL;
} else {
dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
@ -230,7 +234,8 @@ const struct brw_tracked_state gen6_wm_state = {
_NEW_COLOR |
_NEW_BUFFERS |
_NEW_PROGRAM_CONSTANTS |
_NEW_POLYGON),
_NEW_POLYGON |
_NEW_MULTISAMPLE),
.brw = (BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_BATCH),
.cache = (CACHE_NEW_SAMPLER |

10
src/mesa/drivers/dri/i965/gen7_sf_state.c
View file

@ -161,9 +161,9 @@ upload_sf_state(struct brw_context *brw)
float point_size;
/* _NEW_BUFFERS */
bool render_to_fbo = _mesa_is_user_fbo(brw->intel.ctx.DrawBuffer);
bool multisampled = false;
bool multisampled_fbo = false;
if (ctx->DrawBuffer->_ColorDrawBuffers[0])
multisampled = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples > 0;
multisampled_fbo = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples > 0;
dw1 = GEN6_SF_STATISTICS_ENABLE |
GEN6_SF_VIEWPORT_TRANSFORM_ENABLE;
@ -261,7 +261,8 @@ upload_sf_state(struct brw_context *brw)
if (ctx->Line.StippleFlag && intel->is_haswell) {
dw2 |= HSW_SF_LINE_STIPPLE_ENABLE;
}
if (multisampled)
/* _NEW_MULTISAMPLE */
if (multisampled_fbo && ctx->Multisample.Enabled)
dw2 |= GEN6_SF_MSRAST_ON_PATTERN;
/* FINISHME: Last Pixel Enable? Vertex Sub Pixel Precision Select?
@ -309,7 +310,8 @@ const struct brw_tracked_state gen7_sf_state = {
_NEW_LINE |
_NEW_SCISSOR |
_NEW_BUFFERS |
_NEW_POINT),
_NEW_POINT |
_NEW_MULTISAMPLE),
.brw = BRW_NEW_CONTEXT,
.cache = CACHE_NEW_VS_PROG
},

15
src/mesa/drivers/dri/i965/gen7_wm_state.c
View file

@ -39,12 +39,12 @@ upload_wm_state(struct brw_context *brw)
const struct brw_fragment_program *fp =
brw_fragment_program_const(brw->fragment_program);
bool writes_depth = false;
bool multisampled = false;
bool multisampled_fbo = false;
uint32_t dw1, dw2;
/* _NEW_BUFFERS */
if (ctx->DrawBuffer->_ColorDrawBuffers[0])
multisampled = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples > 0;
multisampled_fbo = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples > 0;
dw1 = dw2 = 0;
dw1 |= GEN7_WM_STATISTICS_ENABLE;
@ -79,8 +79,12 @@ upload_wm_state(struct brw_context *brw)
dw1 & GEN7_WM_KILL_ENABLE) {
dw1 |= GEN7_WM_DISPATCH_ENABLE;
}
if (multisampled) {
dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
if (multisampled_fbo) {
/* _NEW_MULTISAMPLE */
if (ctx->Multisample.Enabled)
dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
else
dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
} else {
dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
@ -97,7 +101,8 @@ upload_wm_state(struct brw_context *brw)
const struct brw_tracked_state gen7_wm_state = {
.dirty = {
.mesa = (_NEW_LINE | _NEW_POLYGON |
_NEW_COLOR | _NEW_BUFFERS),
_NEW_COLOR | _NEW_BUFFERS |
_NEW_MULTISAMPLE),
.brw = (BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_BATCH),
.cache = CACHE_NEW_WM_PROG,