mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2025-12-24 13:10:10 +01:00
radv: implement all depth/stencil resolve modes using graphics
When using graphics, the driver doesn't need to decompress HTILE before resolving. This path currently doesn't support layers so we have to fallback to the compute path. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset
parent
e52ad9f845
commit
cdc6efddf9
2 changed files with 614 additions and 0 deletions
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@ -316,6 +316,356 @@ create_resolve_pipeline(struct radv_device *device,
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return result;
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}
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enum {
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DEPTH_RESOLVE,
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STENCIL_RESOLVE
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};
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static const char *
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get_resolve_mode_str(VkResolveModeFlagBitsKHR resolve_mode)
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{
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switch (resolve_mode) {
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case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
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return "zero";
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case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
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return "average";
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case VK_RESOLVE_MODE_MIN_BIT_KHR:
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return "min";
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case VK_RESOLVE_MODE_MAX_BIT_KHR:
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return "max";
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default:
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unreachable("invalid resolve mode");
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}
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}
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static nir_shader *
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build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples,
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int index,
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VkResolveModeFlagBitsKHR resolve_mode)
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{
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nir_builder b;
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char name[64];
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const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
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const struct glsl_type *vec4 = glsl_vec4_type();
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const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D,
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false,
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false,
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GLSL_TYPE_FLOAT);
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snprintf(name, 64, "meta_resolve_fs_%s-%s-%d",
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index == DEPTH_RESOLVE ? "depth" : "stencil",
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get_resolve_mode_str(resolve_mode), samples);
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nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
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b.shader->info.name = ralloc_strdup(b.shader, name);
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nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
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sampler_type, "s_tex");
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input_img->data.descriptor_set = 0;
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input_img->data.binding = 0;
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nir_variable *fs_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "fs_pos_in");
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fs_pos_in->data.location = VARYING_SLOT_POS;
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nir_variable *fs_out = nir_variable_create(b.shader,
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nir_var_shader_out, vec4,
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"f_out");
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fs_out->data.location =
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index == DEPTH_RESOLVE ? FRAG_RESULT_DEPTH : FRAG_RESULT_STENCIL;
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nir_ssa_def *pos_in = nir_load_var(&b, fs_pos_in);
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nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
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nir_intrinsic_set_base(src_offset, 0);
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nir_intrinsic_set_range(src_offset, 8);
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src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
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src_offset->num_components = 2;
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nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
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nir_builder_instr_insert(&b, &src_offset->instr);
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nir_ssa_def *pos_int = nir_f2i32(&b, pos_in);
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nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, &src_offset->dest.ssa), 0x3);
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nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
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nir_alu_type type = index == DEPTH_RESOLVE ? nir_type_float : nir_type_uint;
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nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
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tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
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tex->op = nir_texop_txf_ms;
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tex->src[0].src_type = nir_tex_src_coord;
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tex->src[0].src = nir_src_for_ssa(img_coord);
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tex->src[1].src_type = nir_tex_src_ms_index;
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tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
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tex->src[2].src_type = nir_tex_src_texture_deref;
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tex->src[2].src = nir_src_for_ssa(input_img_deref);
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tex->dest_type = type;
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tex->is_array = false;
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tex->coord_components = 2;
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nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
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nir_builder_instr_insert(&b, &tex->instr);
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nir_ssa_def *outval = &tex->dest.ssa;
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if (resolve_mode != VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR) {
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for (int i = 1; i < samples; i++) {
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nir_tex_instr *tex_add = nir_tex_instr_create(b.shader, 3);
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tex_add->sampler_dim = GLSL_SAMPLER_DIM_MS;
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tex_add->op = nir_texop_txf_ms;
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tex_add->src[0].src_type = nir_tex_src_coord;
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tex_add->src[0].src = nir_src_for_ssa(img_coord);
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tex_add->src[1].src_type = nir_tex_src_ms_index;
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tex_add->src[1].src = nir_src_for_ssa(nir_imm_int(&b, i));
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tex_add->src[2].src_type = nir_tex_src_texture_deref;
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tex_add->src[2].src = nir_src_for_ssa(input_img_deref);
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tex_add->dest_type = type;
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tex_add->is_array = false;
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tex_add->coord_components = 2;
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nir_ssa_dest_init(&tex_add->instr, &tex_add->dest, 4, 32, "tex");
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nir_builder_instr_insert(&b, &tex_add->instr);
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switch (resolve_mode) {
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case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
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assert(index == DEPTH_RESOLVE);
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outval = nir_fadd(&b, outval, &tex_add->dest.ssa);
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break;
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case VK_RESOLVE_MODE_MIN_BIT_KHR:
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if (index == DEPTH_RESOLVE)
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outval = nir_fmin(&b, outval, &tex_add->dest.ssa);
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else
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outval = nir_umin(&b, outval, &tex_add->dest.ssa);
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break;
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case VK_RESOLVE_MODE_MAX_BIT_KHR:
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if (index == DEPTH_RESOLVE)
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outval = nir_fmax(&b, outval, &tex_add->dest.ssa);
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else
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outval = nir_umax(&b, outval, &tex_add->dest.ssa);
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break;
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default:
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unreachable("invalid resolve mode");
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}
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}
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if (resolve_mode == VK_RESOLVE_MODE_AVERAGE_BIT_KHR)
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outval = nir_fdiv(&b, outval, nir_imm_float(&b, samples));
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}
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nir_store_var(&b, fs_out, outval, 0x1);
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return b.shader;
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}
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static VkResult
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create_depth_stencil_resolve_pipeline(struct radv_device *device,
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int samples_log2,
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int index,
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VkResolveModeFlagBitsKHR resolve_mode)
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{
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VkRenderPass *render_pass;
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VkPipeline *pipeline;
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VkFormat src_format;
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VkResult result;
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mtx_lock(&device->meta_state.mtx);
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switch (resolve_mode) {
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case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
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if (index == DEPTH_RESOLVE)
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pipeline = &device->meta_state.resolve_fragment.depth_zero_pipeline;
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else
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pipeline = &device->meta_state.resolve_fragment.stencil_zero_pipeline;
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break;
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case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
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assert(index == DEPTH_RESOLVE);
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pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].average_pipeline;
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break;
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case VK_RESOLVE_MODE_MIN_BIT_KHR:
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if (index == DEPTH_RESOLVE)
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pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].min_pipeline;
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else
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pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].min_pipeline;
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break;
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case VK_RESOLVE_MODE_MAX_BIT_KHR:
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if (index == DEPTH_RESOLVE)
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pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].max_pipeline;
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else
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pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].max_pipeline;
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break;
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default:
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unreachable("invalid resolve mode");
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}
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if (*pipeline) {
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mtx_unlock(&device->meta_state.mtx);
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return VK_SUCCESS;
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}
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struct radv_shader_module fs = { .nir = NULL };
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struct radv_shader_module vs = { .nir = NULL };
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uint32_t samples = 1 << samples_log2;
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vs.nir = build_nir_vertex_shader();
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fs.nir = build_depth_stencil_resolve_fragment_shader(device, samples,
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index, resolve_mode);
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VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
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{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_VERTEX_BIT,
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.module = radv_shader_module_to_handle(&vs),
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.pName = "main",
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.pSpecializationInfo = NULL
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}, {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_FRAGMENT_BIT,
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.module = radv_shader_module_to_handle(&fs),
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.pName = "main",
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.pSpecializationInfo = NULL
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},
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};
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if (index == DEPTH_RESOLVE) {
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src_format = VK_FORMAT_D32_SFLOAT;
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render_pass = &device->meta_state.resolve_fragment.depth_render_pass;
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} else {
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render_pass = &device->meta_state.resolve_fragment.stencil_render_pass;
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src_format = VK_FORMAT_S8_UINT;
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}
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if (!*render_pass) {
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result = radv_CreateRenderPass(radv_device_to_handle(device),
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&(VkRenderPassCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
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.attachmentCount = 1,
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.pAttachments = &(VkAttachmentDescription) {
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.format = src_format,
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.loadOp = VK_ATTACHMENT_LOAD_OP_DONT_CARE,
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.storeOp = VK_ATTACHMENT_LOAD_OP_DONT_CARE,
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.stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
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.stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
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.initialLayout = VK_IMAGE_LAYOUT_GENERAL,
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.finalLayout = VK_IMAGE_LAYOUT_GENERAL,
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},
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.subpassCount = 1,
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.pSubpasses = &(VkSubpassDescription) {
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.pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
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.inputAttachmentCount = 0,
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.colorAttachmentCount = 0,
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.pColorAttachments = NULL,
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.pResolveAttachments = NULL,
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.pDepthStencilAttachment = &(VkAttachmentReference) {
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.attachment = 0,
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.layout = VK_IMAGE_LAYOUT_GENERAL,
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},
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.preserveAttachmentCount = 0,
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.pPreserveAttachments = NULL,
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},
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.dependencyCount = 0,
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}, &device->meta_state.alloc, render_pass);
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}
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VkStencilOp stencil_op =
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index == DEPTH_RESOLVE ? VK_STENCIL_OP_KEEP : VK_STENCIL_OP_REPLACE;
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VkPipelineDepthStencilStateCreateInfo depth_stencil_state = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
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.depthTestEnable = true,
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.depthWriteEnable = index == DEPTH_RESOLVE,
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.stencilTestEnable = index == STENCIL_RESOLVE,
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.depthCompareOp = VK_COMPARE_OP_ALWAYS,
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.front = {
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.failOp = stencil_op,
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.passOp = stencil_op,
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.depthFailOp = stencil_op,
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.compareOp = VK_COMPARE_OP_ALWAYS,
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},
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.back = {
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.failOp = stencil_op,
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.passOp = stencil_op,
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.depthFailOp = stencil_op,
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.compareOp = VK_COMPARE_OP_ALWAYS,
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}
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};
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const VkPipelineVertexInputStateCreateInfo *vi_create_info;
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vi_create_info = &normal_vi_create_info;
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const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
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.stageCount = ARRAY_SIZE(pipeline_shader_stages),
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.pStages = pipeline_shader_stages,
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.pVertexInputState = vi_create_info,
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.pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
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.topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
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.primitiveRestartEnable = false,
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},
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.pViewportState = &(VkPipelineViewportStateCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
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.viewportCount = 1,
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.scissorCount = 1,
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},
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.pDepthStencilState = &depth_stencil_state,
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.pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
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.rasterizerDiscardEnable = false,
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.polygonMode = VK_POLYGON_MODE_FILL,
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.cullMode = VK_CULL_MODE_NONE,
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.frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
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},
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.pMultisampleState = NULL,
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.pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
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.attachmentCount = 0,
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.pAttachments = (VkPipelineColorBlendAttachmentState []) {
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{ .colorWriteMask =
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VK_COLOR_COMPONENT_A_BIT |
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VK_COLOR_COMPONENT_R_BIT |
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VK_COLOR_COMPONENT_G_BIT |
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VK_COLOR_COMPONENT_B_BIT },
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}
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},
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.pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
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.dynamicStateCount = 9,
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.pDynamicStates = (VkDynamicState[]) {
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VK_DYNAMIC_STATE_VIEWPORT,
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VK_DYNAMIC_STATE_SCISSOR,
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VK_DYNAMIC_STATE_LINE_WIDTH,
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VK_DYNAMIC_STATE_DEPTH_BIAS,
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VK_DYNAMIC_STATE_BLEND_CONSTANTS,
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VK_DYNAMIC_STATE_DEPTH_BOUNDS,
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VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
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VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
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VK_DYNAMIC_STATE_STENCIL_REFERENCE,
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},
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},
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.flags = 0,
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.layout = device->meta_state.resolve_fragment.p_layout,
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.renderPass = *render_pass,
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.subpass = 0,
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};
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const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
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.use_rectlist = true
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};
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result = radv_graphics_pipeline_create(radv_device_to_handle(device),
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radv_pipeline_cache_to_handle(&device->meta_state.cache),
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&vk_pipeline_info, &radv_pipeline_info,
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&device->meta_state.alloc,
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pipeline);
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ralloc_free(vs.nir);
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ralloc_free(fs.nir);
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mtx_unlock(&device->meta_state.mtx);
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return result;
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}
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VkResult
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radv_device_init_meta_resolve_fragment_state(struct radv_device *device, bool on_demand)
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{
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@ -334,8 +684,43 @@ radv_device_init_meta_resolve_fragment_state(struct radv_device *device, bool on
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if (res != VK_SUCCESS)
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goto fail;
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}
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res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
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VK_RESOLVE_MODE_AVERAGE_BIT_KHR);
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if (res != VK_SUCCESS)
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goto fail;
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res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
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VK_RESOLVE_MODE_MIN_BIT_KHR);
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if (res != VK_SUCCESS)
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goto fail;
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res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
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VK_RESOLVE_MODE_MAX_BIT_KHR);
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if (res != VK_SUCCESS)
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goto fail;
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res = create_depth_stencil_resolve_pipeline(device, i, STENCIL_RESOLVE,
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VK_RESOLVE_MODE_MIN_BIT_KHR);
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if (res != VK_SUCCESS)
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goto fail;
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res = create_depth_stencil_resolve_pipeline(device, i, STENCIL_RESOLVE,
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VK_RESOLVE_MODE_MAX_BIT_KHR);
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if (res != VK_SUCCESS)
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goto fail;
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}
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res = create_depth_stencil_resolve_pipeline(device, 0, DEPTH_RESOLVE,
|
||||
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR);
|
||||
if (res != VK_SUCCESS)
|
||||
goto fail;
|
||||
|
||||
res = create_depth_stencil_resolve_pipeline(device, 0, STENCIL_RESOLVE,
|
||||
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR);
|
||||
if (res != VK_SUCCESS)
|
||||
goto fail;
|
||||
|
||||
return VK_SUCCESS;
|
||||
fail:
|
||||
radv_device_finish_meta_resolve_fragment_state(device);
|
||||
|
|
@ -357,8 +742,42 @@ radv_device_finish_meta_resolve_fragment_state(struct radv_device *device)
|
|||
state->resolve_fragment.rc[i].pipeline[j],
|
||||
&state->alloc);
|
||||
}
|
||||
|
||||
radv_DestroyPipeline(radv_device_to_handle(device),
|
||||
state->resolve_fragment.depth[i].average_pipeline,
|
||||
&state->alloc);
|
||||
|
||||
radv_DestroyPipeline(radv_device_to_handle(device),
|
||||
state->resolve_fragment.depth[i].max_pipeline,
|
||||
&state->alloc);
|
||||
|
||||
radv_DestroyPipeline(radv_device_to_handle(device),
|
||||
state->resolve_fragment.depth[i].min_pipeline,
|
||||
&state->alloc);
|
||||
|
||||
radv_DestroyPipeline(radv_device_to_handle(device),
|
||||
state->resolve_fragment.stencil[i].max_pipeline,
|
||||
&state->alloc);
|
||||
|
||||
radv_DestroyPipeline(radv_device_to_handle(device),
|
||||
state->resolve_fragment.stencil[i].min_pipeline,
|
||||
&state->alloc);
|
||||
}
|
||||
|
||||
radv_DestroyRenderPass(radv_device_to_handle(device),
|
||||
state->resolve_fragment.depth_render_pass,
|
||||
&state->alloc);
|
||||
radv_DestroyRenderPass(radv_device_to_handle(device),
|
||||
state->resolve_fragment.stencil_render_pass,
|
||||
&state->alloc);
|
||||
|
||||
radv_DestroyPipeline(radv_device_to_handle(device),
|
||||
state->resolve_fragment.depth_zero_pipeline,
|
||||
&state->alloc);
|
||||
radv_DestroyPipeline(radv_device_to_handle(device),
|
||||
state->resolve_fragment.stencil_zero_pipeline,
|
||||
&state->alloc);
|
||||
|
||||
radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
|
||||
state->resolve_fragment.ds_layout,
|
||||
&state->alloc);
|
||||
|
|
@ -461,6 +880,111 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
|
|||
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
|
||||
}
|
||||
|
||||
static void
|
||||
emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer,
|
||||
struct radv_image_view *src_iview,
|
||||
struct radv_image_view *dst_iview,
|
||||
const VkOffset2D *src_offset,
|
||||
const VkOffset2D *dst_offset,
|
||||
const VkExtent2D *resolve_extent,
|
||||
VkImageAspectFlags aspects,
|
||||
VkResolveModeFlagBitsKHR resolve_mode)
|
||||
{
|
||||
struct radv_device *device = cmd_buffer->device;
|
||||
const uint32_t samples = src_iview->image->info.samples;
|
||||
const uint32_t samples_log2 = ffs(samples) - 1;
|
||||
VkPipeline *pipeline;
|
||||
|
||||
radv_meta_push_descriptor_set(cmd_buffer,
|
||||
VK_PIPELINE_BIND_POINT_GRAPHICS,
|
||||
cmd_buffer->device->meta_state.resolve_fragment.p_layout,
|
||||
0, /* set */
|
||||
1, /* descriptorWriteCount */
|
||||
(VkWriteDescriptorSet[]) {
|
||||
{
|
||||
.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
||||
.dstBinding = 0,
|
||||
.dstArrayElement = 0,
|
||||
.descriptorCount = 1,
|
||||
.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
|
||||
.pImageInfo = (VkDescriptorImageInfo[]) {
|
||||
{
|
||||
.sampler = VK_NULL_HANDLE,
|
||||
.imageView = radv_image_view_to_handle(src_iview),
|
||||
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
|
||||
},
|
||||
}
|
||||
},
|
||||
});
|
||||
|
||||
unsigned push_constants[2] = {
|
||||
src_offset->x - dst_offset->x,
|
||||
src_offset->y - dst_offset->y,
|
||||
};
|
||||
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
|
||||
device->meta_state.resolve_fragment.p_layout,
|
||||
VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8,
|
||||
push_constants);
|
||||
|
||||
switch (resolve_mode) {
|
||||
case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
|
||||
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
|
||||
pipeline = &device->meta_state.resolve_fragment.depth_zero_pipeline;
|
||||
else
|
||||
pipeline = &device->meta_state.resolve_fragment.stencil_zero_pipeline;
|
||||
break;
|
||||
case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
|
||||
assert(aspects == VK_IMAGE_ASPECT_DEPTH_BIT);
|
||||
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].average_pipeline;
|
||||
break;
|
||||
case VK_RESOLVE_MODE_MIN_BIT_KHR:
|
||||
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
|
||||
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].min_pipeline;
|
||||
else
|
||||
pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].min_pipeline;
|
||||
break;
|
||||
case VK_RESOLVE_MODE_MAX_BIT_KHR:
|
||||
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
|
||||
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].max_pipeline;
|
||||
else
|
||||
pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].max_pipeline;
|
||||
break;
|
||||
default:
|
||||
unreachable("invalid resolve mode");
|
||||
}
|
||||
|
||||
if (!*pipeline) {
|
||||
int index = aspects == VK_IMAGE_ASPECT_DEPTH_BIT ? DEPTH_RESOLVE : STENCIL_RESOLVE;
|
||||
VkResult ret;
|
||||
|
||||
ret = create_depth_stencil_resolve_pipeline(device, samples_log2,
|
||||
index, resolve_mode);
|
||||
if (ret != VK_SUCCESS) {
|
||||
cmd_buffer->record_result = ret;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
|
||||
VK_PIPELINE_BIND_POINT_GRAPHICS, *pipeline);
|
||||
|
||||
radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
|
||||
.x = dst_offset->x,
|
||||
.y = dst_offset->y,
|
||||
.width = resolve_extent->width,
|
||||
.height = resolve_extent->height,
|
||||
.minDepth = 0.0f,
|
||||
.maxDepth = 1.0f
|
||||
});
|
||||
|
||||
radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
|
||||
.offset = *dst_offset,
|
||||
.extent = *resolve_extent,
|
||||
});
|
||||
|
||||
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
|
||||
}
|
||||
|
||||
void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
|
||||
struct radv_image *src_image,
|
||||
VkImageLayout src_image_layout,
|
||||
|
|
@ -653,3 +1177,75 @@ radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer)
|
|||
|
||||
radv_meta_restore(&saved_state, cmd_buffer);
|
||||
}
|
||||
|
||||
/**
|
||||
* Depth/stencil resolves for the current subpass.
|
||||
*/
|
||||
void
|
||||
radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
|
||||
VkImageAspectFlags aspects,
|
||||
VkResolveModeFlagBitsKHR resolve_mode)
|
||||
{
|
||||
struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
|
||||
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
|
||||
struct radv_meta_saved_state saved_state;
|
||||
struct radv_subpass_barrier barrier;
|
||||
|
||||
/* Resolves happen before the end-of-subpass barriers get executed,
|
||||
* so we have to make the attachment shader-readable */
|
||||
barrier.src_stage_mask = VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
|
||||
barrier.src_access_mask = VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
|
||||
barrier.dst_access_mask = VK_ACCESS_INPUT_ATTACHMENT_READ_BIT;
|
||||
radv_subpass_barrier(cmd_buffer, &barrier);
|
||||
|
||||
radv_decompress_resolve_subpass_src(cmd_buffer);
|
||||
|
||||
radv_meta_save(&saved_state, cmd_buffer,
|
||||
RADV_META_SAVE_GRAPHICS_PIPELINE |
|
||||
RADV_META_SAVE_CONSTANTS |
|
||||
RADV_META_SAVE_DESCRIPTORS);
|
||||
|
||||
struct radv_subpass_attachment src_att = *subpass->depth_stencil_attachment;
|
||||
struct radv_subpass_attachment dst_att = *subpass->ds_resolve_attachment;
|
||||
|
||||
struct radv_image_view *src_iview =
|
||||
cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
|
||||
struct radv_image *src_image = src_iview->image;
|
||||
struct radv_image_view *dst_iview =
|
||||
cmd_buffer->state.framebuffer->attachments[dst_att.attachment].attachment;
|
||||
|
||||
struct radv_subpass resolve_subpass = {
|
||||
.color_count = 0,
|
||||
.color_attachments = NULL,
|
||||
.depth_stencil_attachment = (struct radv_subpass_attachment *) { &dst_att },
|
||||
};
|
||||
|
||||
radv_cmd_buffer_set_subpass(cmd_buffer, &resolve_subpass);
|
||||
|
||||
struct radv_image_view tsrc_iview;
|
||||
radv_image_view_init(&tsrc_iview, cmd_buffer->device,
|
||||
&(VkImageViewCreateInfo) {
|
||||
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
||||
.image = radv_image_to_handle(src_image),
|
||||
.viewType = radv_meta_get_view_type(src_image),
|
||||
.format = src_iview->vk_format,
|
||||
.subresourceRange = {
|
||||
.aspectMask = aspects,
|
||||
.baseMipLevel = 0,
|
||||
.levelCount = 1,
|
||||
.baseArrayLayer = 0,
|
||||
.layerCount = 1,
|
||||
},
|
||||
});
|
||||
|
||||
emit_depth_stencil_resolve(cmd_buffer, &tsrc_iview, dst_iview,
|
||||
&(VkOffset2D) { 0, 0 },
|
||||
&(VkOffset2D) { 0, 0 },
|
||||
&(VkExtent2D) { fb->width, fb->height },
|
||||
aspects,
|
||||
resolve_mode);
|
||||
|
||||
radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
|
||||
|
||||
radv_meta_restore(&saved_state, cmd_buffer);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -587,6 +587,21 @@ struct radv_meta_state {
|
|||
VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
|
||||
VkPipeline pipeline[NUM_META_FS_KEYS];
|
||||
} rc[MAX_SAMPLES_LOG2];
|
||||
|
||||
VkRenderPass depth_render_pass;
|
||||
VkPipeline depth_zero_pipeline;
|
||||
struct {
|
||||
VkPipeline average_pipeline;
|
||||
VkPipeline max_pipeline;
|
||||
VkPipeline min_pipeline;
|
||||
} depth[MAX_SAMPLES_LOG2];
|
||||
|
||||
VkRenderPass stencil_render_pass;
|
||||
VkPipeline stencil_zero_pipeline;
|
||||
struct {
|
||||
VkPipeline max_pipeline;
|
||||
VkPipeline min_pipeline;
|
||||
} stencil[MAX_SAMPLES_LOG2];
|
||||
} resolve_fragment;
|
||||
|
||||
struct {
|
||||
|
|
@ -1242,6 +1257,9 @@ void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
|
|||
void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
|
||||
void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
|
||||
void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
|
||||
void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
|
||||
VkImageAspectFlags aspects,
|
||||
VkResolveModeFlagBitsKHR resolve_mode);
|
||||
void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
|
||||
unsigned radv_get_default_max_sample_dist(int log_samples);
|
||||
void radv_device_init_msaa(struct radv_device *device);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue