radeonsi: handle 64-bit loads earlier in fetch_constant

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-10-08 18:20:38 +02:00
parent ee0e1a47ce
commit cdb21dfffa

View file

@ -1977,7 +1977,6 @@ static LLVMValueRef fetch_constant(
unsigned buf, idx; unsigned buf, idx;
LLVMValueRef addr, bufp; LLVMValueRef addr, bufp;
LLVMValueRef result;
if (swizzle == LP_CHAN_ALL) { if (swizzle == LP_CHAN_ALL) {
unsigned chan; unsigned chan;
@ -1988,6 +1987,15 @@ static LLVMValueRef fetch_constant(
return lp_build_gather_values(&ctx->gallivm, values, 4); return lp_build_gather_values(&ctx->gallivm, values, 4);
} }
/* Split 64-bit loads. */
if (tgsi_type_is_64bit(type)) {
LLVMValueRef lo, hi;
lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
}
assert(reg->Register.Dimension); assert(reg->Register.Dimension);
buf = reg->Dimension.Index; buf = reg->Dimension.Index;
idx = reg->Register.Index * 4 + swizzle; idx = reg->Register.Index * 4 + swizzle;
@ -2010,21 +2018,7 @@ static LLVMValueRef fetch_constant(
addr = LLVMConstInt(ctx->i32, idx * 4, 0); addr = LLVMConstInt(ctx->i32, idx * 4, 0);
} }
result = buffer_load_const(ctx, bufp, addr); return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
if (!tgsi_type_is_64bit(type))
result = bitcast(bld_base, type, result);
else {
LLVMValueRef addr2, result2;
addr2 = lp_build_add(&bld_base->uint_bld, addr,
LLVMConstInt(ctx->i32, 4, 0));
result2 = buffer_load_const(ctx, bufp, addr2);
result = si_llvm_emit_fetch_64bit(bld_base, type,
result, result2);
}
return result;
} }
/* Upper 16 bits must be zero. */ /* Upper 16 bits must be zero. */