radeonsi/vcn: Add vcn_5_0_2 support

Add support for Radeosi VCN 5_0_2 version

Signed-off-by: Sonny Jiang <sonjiang@amd.com>
This commit is contained in:
Sonny Jiang 2026-01-19 12:15:34 -05:00 committed by Sonny Jiang
parent 439c1123b0
commit cd998a4c0e
5 changed files with 22 additions and 7 deletions

View file

@ -482,7 +482,7 @@ ac_fill_hw_ip_info(struct radeon_info *info, const struct drm_amdgpu_info_device
return false;
info->ip[ip_type].num_queues = util_bitcount(ip_info->available_rings);
} else {
} else if (ip_type != 0) {
return false;
}
@ -852,6 +852,9 @@ ac_identify_chip(struct radeon_info *info, const struct drm_amdgpu_info_device *
case VCN_IP_VERSION(5, 0, 1):
info->vcn_ip_version = VCN_5_0_1;
break;
case VCN_IP_VERSION(5, 0, 2):
info->vcn_ip_version = VCN_5_0_2;
break;
case VCN_IP_VERSION(5, 3, 0):
info->vcn_ip_version = VCN_5_3_0;
break;

View file

@ -623,7 +623,8 @@ bool ac_get_supported_modifiers(const struct radeon_info *info,
ADD_MOD(DRM_FORMAT_MOD_LINEAR)
break;
}
case GFX12: {
case GFX12:
case GFX12_1: {
/* Chip properties no longer affect tiling, and there is no distinction between displayable
* and non-displayable anymore. (DCC settings may affect displayability though)
*

View file

@ -2010,7 +2010,7 @@ vcn_build_decode_cmd(struct ac_video_dec *decoder, struct ac_video_dec_decode_cm
decode_flags |= RDECODE_FLAGS_LOW_LATENCY_MASK;
if (cmd->tier == AC_VIDEO_DEC_TIER0) {
if (dec->vcn_version == VCN_5_0_0)
if (dec->vcn_version >= VCN_5_0_0)
decode->db_swizzle_mode = RDECODE_VCN5_256B_D;
} else if (cmd->tier == AC_VIDEO_DEC_TIER1) {
decode_flags |= RDECODE_FLAGS_USE_DYNAMIC_DPB_MASK | RDECODE_FLAGS_USE_PAL_MASK;
@ -2050,6 +2050,8 @@ vcn_build_decode_cmd(struct ac_video_dec *decoder, struct ac_video_dec_decode_cm
decode_flags |= RDECODE_FLAGS_USE_DYNAMIC_DPB_MASK;
decode->db_swizzle_mode = cur->planes[0].surf->u.gfx9.swizzle_mode;
if (dec->vcn_version == VCN_5_0_2)
decode->db_swizzle_mode = RDECODE_VCN5_256B_D;
dynamic_dpb_t2->dpbArraySize = ref_id_size;
dynamic_dpb_t2->dpbCurrLo = cur->planes[0].va;
@ -2351,6 +2353,10 @@ ac_vcn_create_video_decoder(const struct radeon_info *info, struct ac_video_dec_
dec->addr_mode = RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX11;
dec->av1_version = RDECODE_AV1_VER_2;
break;
case VCN_5_0_2:
dec->addr_mode = RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX11;
dec->av1_version = RDECODE_AV1_VER_2;
break;
default:
assert(!"unsupported vcn version");
}

View file

@ -223,6 +223,7 @@ enum vcn_version{
VCN_5_0_0,
VCN_5_0_1,
VCN_5_0_2,
VCN_5_3_0,
};

View file

@ -109,7 +109,8 @@ static int si_video_get_param(struct pipe_screen *screen, enum pipe_video_profil
return 0;
if (sscreen->info.vcn_ip_version == VCN_4_0_3 ||
sscreen->info.vcn_ip_version == VCN_5_0_1)
sscreen->info.vcn_ip_version == VCN_5_0_1 ||
sscreen->info.vcn_ip_version == VCN_5_0_2)
return 0;
switch (param) {
@ -495,7 +496,8 @@ static int si_video_get_param(struct pipe_screen *screen, enum pipe_video_profil
case PIPE_VIDEO_CAP_ROI_CROP_DEC:
if (codec == PIPE_VIDEO_FORMAT_JPEG &&
(sscreen->info.vcn_ip_version == VCN_4_0_3 ||
sscreen->info.vcn_ip_version == VCN_5_0_1))
sscreen->info.vcn_ip_version == VCN_5_0_1 ||
sscreen->info.vcn_ip_version == VCN_5_0_2))
return true;
return false;
case PIPE_VIDEO_CAP_SKIP_CLEAR_SURFACE:
@ -562,7 +564,8 @@ static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_for
case PIPE_FORMAT_A8R8G8B8_UNORM:
case PIPE_FORMAT_R8_G8_B8_UNORM:
if (sscreen->info.vcn_ip_version == VCN_4_0_3 ||
sscreen->info.vcn_ip_version == VCN_5_0_1)
sscreen->info.vcn_ip_version == VCN_5_0_1 ||
sscreen->info.vcn_ip_version == VCN_5_0_2)
return true;
else
return false;
@ -577,7 +580,8 @@ static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_for
((profile == PIPE_VIDEO_PROFILE_AV1_MAIN) &&
(sscreen->info.vcn_ip_version >= VCN_4_0_0 &&
sscreen->info.vcn_ip_version != VCN_4_0_3 &&
sscreen->info.vcn_ip_version != VCN_5_0_1))))
sscreen->info.vcn_ip_version != VCN_5_0_1 &&
sscreen->info.vcn_ip_version != VCN_5_0_2))))
return (format == PIPE_FORMAT_P010 || format == PIPE_FORMAT_NV12);