From cd71cca234d4463bdb6e1e2f911f7654626537bb Mon Sep 17 00:00:00 2001 From: Calder Young Date: Thu, 9 Apr 2026 15:12:11 -0700 Subject: [PATCH] anv: Fix support for indirect SBTs on Xe3+ Fixes: 6deb195 ("anv: Update RT dispatch globals to use 64bit data structure") (cherry picked from commit 6aabe5482e51ec28126d4af5285936c04b247a34) Part-of: --- .pick_status.json | 2 +- src/intel/genxml/meson.build | 3 ++ src/intel/vulkan/genX_cmd_compute.c | 78 +++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+), 1 deletion(-) diff --git a/.pick_status.json b/.pick_status.json index dd840c4c720..98e19a63b1b 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -2124,7 +2124,7 @@ "description": "anv: Fix support for indirect SBTs on Xe3+", "nominated": true, "nomination_type": 2, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "6deb1950a4b632b9c1b0af88ad949a4dcf6d4257", "notes": null diff --git a/src/intel/genxml/meson.build b/src/intel/genxml/meson.build index 72bfd73b7f6..cac206a95c2 100644 --- a/src/intel/genxml/meson.build +++ b/src/intel/genxml/meson.build @@ -82,6 +82,9 @@ genX_bits_included_symbols = [ 'RT_DISPATCH_GLOBALS::Hit Group Table', 'RT_DISPATCH_GLOBALS::Miss Group Table', 'RT_DISPATCH_GLOBALS::Callable Group Table', + 'RT_DISPATCH_GLOBALS::Hit Group Stride', + 'RT_DISPATCH_GLOBALS::Miss Group Stride', + 'RT_DISPATCH_GLOBALS::Callable Group Stride', 'RT_DISPATCH_GLOBALS::Launch Width', 'RT_DISPATCH_GLOBALS::Launch Height', 'RT_DISPATCH_GLOBALS::Launch Depth', diff --git a/src/intel/vulkan/genX_cmd_compute.c b/src/intel/vulkan/genX_cmd_compute.c index d51912bd714..2808ce42187 100644 --- a/src/intel/vulkan/genX_cmd_compute.c +++ b/src/intel/vulkan/genX_cmd_compute.c @@ -1030,6 +1030,7 @@ cmd_buffer_emit_rt_dispatch_globals(struct anv_cmd_buffer *cmd_buffer, return rtdg_state; } +#if GFX_VER < 30 static struct mi_value mi_build_sbt_entry(struct mi_builder *b, uint64_t addr_field_addr, @@ -1041,6 +1042,7 @@ mi_build_sbt_entry(struct mi_builder *b, mi_ishl_imm(b, mi_mem32(anv_address_from_u64(stride_field_addr)), 48)); } +#endif static struct anv_state cmd_buffer_emit_rt_dispatch_globals_indirect(struct anv_cmd_buffer *cmd_buffer, @@ -1086,6 +1088,7 @@ cmd_buffer_emit_rt_dispatch_globals_indirect(struct anv_cmd_buffer *cmd_buffer, /* Fill the MissGroupTable, HitGroupTable & CallableGroupTable fields of * RT_DISPATCH_GLOBALS using the mi_builder. */ +#if GFX_VER < 30 mi_store(&b, mi_mem64( anv_address_add( @@ -1122,7 +1125,82 @@ cmd_buffer_emit_rt_dispatch_globals_indirect(struct anv_cmd_buffer *cmd_buffer, params->indirect_sbts_addr + offsetof(VkTraceRaysIndirectCommand2KHR, callableShaderBindingTableStride))); +#else + mi_store(&b, + mi_mem64( + anv_address_add( + rtdg_addr, + GENX(RT_DISPATCH_GLOBALS_MissGroupTable_start) / 8)), + mi_mem64( + anv_address_from_u64( + params->indirect_sbts_addr + + offsetof(VkTraceRaysIndirectCommand2KHR, + missShaderBindingTableAddress)))); + mi_store(&b, + mi_mem64( + anv_address_add( + rtdg_addr, + GENX(RT_DISPATCH_GLOBALS_HitGroupTable_start) / 8)), + mi_mem64( + anv_address_from_u64( + params->indirect_sbts_addr + + offsetof(VkTraceRaysIndirectCommand2KHR, + hitShaderBindingTableAddress)))); + mi_store(&b, + mi_mem64( + anv_address_add( + rtdg_addr, + GENX(RT_DISPATCH_GLOBALS_CallableGroupTable_start) / 8)), + mi_mem64( + anv_address_from_u64( + params->indirect_sbts_addr + + offsetof(VkTraceRaysIndirectCommand2KHR, + callableShaderBindingTableAddress)))); + /* The hit and miss group stride on Xe3+ are smashed into the same dword, + * along with the max bvh levels. + */ + struct mi_value hit_stride_bits = + mi_ishl_imm(&b, + mi_iand(&b, + mi_mem32( + anv_address_from_u64( + params->indirect_sbts_addr + + offsetof(VkTraceRaysIndirectCommand2KHR, + hitShaderBindingTableStride))), + mi_imm(BITFIELD_MASK(13))), + GENX(RT_DISPATCH_GLOBALS_HitGroupStride_start) % 32); + struct mi_value miss_stride_bits = + mi_ishl_imm(&b, + mi_iand(&b, + mi_mem32( + anv_address_from_u64( + params->indirect_sbts_addr + + offsetof(VkTraceRaysIndirectCommand2KHR, + missShaderBindingTableStride))), + mi_imm(BITFIELD_MASK(13))), + GENX(RT_DISPATCH_GLOBALS_MissGroupStride_start) % 32); + mi_store(&b, + mi_mem32( + anv_address_add( + rtdg_addr, + GENX(RT_DISPATCH_GLOBALS_HitGroupStride_start) / 32 * 4)), + mi_ior(&b, + mi_ior(&b, hit_stride_bits, miss_stride_bits), + mi_imm(BRW_RT_MAX_BVH_LEVELS))); + mi_store(&b, + mi_mem32( + anv_address_add( + rtdg_addr, + GENX(RT_DISPATCH_GLOBALS_CallableGroupStride_start) / 8)), + mi_iand(&b, + mi_mem32( + anv_address_from_u64( + params->indirect_sbts_addr + + offsetof(VkTraceRaysIndirectCommand2KHR, + callableShaderBindingTableStride))), + mi_imm(BITFIELD_MASK(13)))); +#endif return rtdg_state; }