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freedreno: Rename and document tess primid-related sysvals

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DSPATCHID and HSPATCHID, which we mapped gl_PrimitiveID to, are actually
relative to the current subdraw. Subdraws aren't supported yet by turnip
but they are by freedreno for indirect draws.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12166>
This commit is contained in:
Connor Abbott 2021-07-29 17:40:17 +02:00 • committed by Marge Bot
parent 97b0981ed9
commit cd687c4e3b
6 changed files with 40 additions and 31 deletions
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8
src/freedreno/.gitlab-ci/reference/crash.log
View file

@ -6342,8 +6342,8 @@ clusters:
00000000 PC_MULTIVIEW_CNTL: { VIEWS = 0 }
00000000 VFD_CONTROL_0: { FETCH_CNT = 0 | DECODE_CNT = 0 }
fcfcfcfc VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x }
0000fcfc VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
fcfcfcfc VFD_CONTROL_3: { UNK0 = r63.x | REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
0000fcfc VFD_CONTROL_2: { REGID_HSRELPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
fcfcfcfc VFD_CONTROL_3: { REGID_DSPRIMID = r63.x | REGID_DSRELPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
000000fc VFD_CONTROL_4: { UNK0 = r63.x }
0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x }
00000000 VFD_CONTROL_6: { 0 }
@ -6602,8 +6602,8 @@ clusters:
00000000 PC_MULTIVIEW_CNTL: { VIEWS = 0 }
00000000 VFD_CONTROL_0: { FETCH_CNT = 0 | DECODE_CNT = 0 }
fcfcfcfc VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x }
0000fcfc VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
fcfcfcfc VFD_CONTROL_3: { UNK0 = r63.x | REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
0000fcfc VFD_CONTROL_2: { REGID_HSRELPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
fcfcfcfc VFD_CONTROL_3: { REGID_DSPRIMID = r63.x | REGID_DSRELPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
000000fc VFD_CONTROL_4: { UNK0 = r63.x }
0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x }
00000000 VFD_CONTROL_6: { 0 }

8
src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
View file

@ -925,8 +925,8 @@ t4 write SP_HS_WAVE_INPUT_SIZE (a831)
0000000001054258: 0000: 48a83101 00000000
t4 write VFD_CONTROL_1 (a001)
VFD_CONTROL_1: { REGID4VTX = r2.y | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x }
VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
VFD_CONTROL_3: { UNK0 = r63.x | REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
VFD_CONTROL_2: { REGID_HSRELPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
VFD_CONTROL_3: { REGID_DSPRIMID = r63.x | REGID_DSRELPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
VFD_CONTROL_4: { UNK0 = r63.x }
VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x }
VFD_CONTROL_6: { 0 }
@ -1429,8 +1429,8 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
!+ 00000008 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 8 | CLIP_MASK = 0 }
!+ 00000303 VFD_CONTROL_0: { FETCH_CNT = 3 | DECODE_CNT = 3 }
!+ fcfcfc09 VFD_CONTROL_1: { REGID4VTX = r2.y | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x }
!+ 0000fcfc VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
!+ fcfcfcfc VFD_CONTROL_3: { UNK0 = r63.x | REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
!+ 0000fcfc VFD_CONTROL_2: { REGID_HSRELPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
!+ fcfcfcfc VFD_CONTROL_3: { REGID_DSPRIMID = r63.x | REGID_DSRELPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
!+ 000000fc VFD_CONTROL_4: { UNK0 = r63.x }
!+ 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x }
+ 00000000 VFD_CONTROL_6: { 0 }

16
src/freedreno/.gitlab-ci/reference/fd-clouds.log
View file

@ -745,8 +745,8 @@ t4 write VPC_UNKNOWN_9107 (9107)
0000000001121148: 0000: 48910701 00000000
t4 write VFD_CONTROL_1 (a001)
VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x }
VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
VFD_CONTROL_3: { UNK0 = r63.x | REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
VFD_CONTROL_2: { REGID_HSRELPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
VFD_CONTROL_3: { REGID_DSPRIMID = r63.x | REGID_DSRELPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
VFD_CONTROL_4: { UNK0 = r63.x }
VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x }
VFD_CONTROL_6: { 0 }
@ -1058,8 +1058,8 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ 00000000 PC_UNKNOWN_9E72: 0
!+ 00000101 VFD_CONTROL_0: { FETCH_CNT = 1 | DECODE_CNT = 1 }
!+ fcfcfcfc VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x }
!+ 0000fcfc VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
!+ fcfcfcfc VFD_CONTROL_3: { UNK0 = r63.x | REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
!+ 0000fcfc VFD_CONTROL_2: { REGID_HSRELPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
!+ fcfcfcfc VFD_CONTROL_3: { REGID_DSPRIMID = r63.x | REGID_DSRELPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
!+ 000000fc VFD_CONTROL_4: { UNK0 = r63.x }
!+ 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x }
+ 00000000 VFD_CONTROL_6: { 0 }
@ -4889,8 +4889,8 @@ t7 opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords)
0000000001120164: 0000: 70348003 16320000 01013000 00000000
t4 write VFD_CONTROL_1 (a001)
VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x }
VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
VFD_CONTROL_3: { UNK0 = r63.x | REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
VFD_CONTROL_2: { REGID_HSRELPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
VFD_CONTROL_3: { REGID_DSPRIMID = r63.x | REGID_DSRELPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
VFD_CONTROL_4: { UNK0 = r63.x }
VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x }
VFD_CONTROL_6: { 0 }
@ -5261,8 +5261,8 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ 00000000 PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 }
+ 00000101 VFD_CONTROL_0: { FETCH_CNT = 1 | DECODE_CNT = 1 }
+ fcfcfcfc VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x }
+ 0000fcfc VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
+ fcfcfcfc VFD_CONTROL_3: { UNK0 = r63.x | REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
+ 0000fcfc VFD_CONTROL_2: { REGID_HSRELPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
+ fcfcfcfc VFD_CONTROL_3: { REGID_DSPRIMID = r63.x | REGID_DSRELPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x }
+ 000000fc VFD_CONTROL_4: { UNK0 = r63.x }
+ 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x }
+ 00000000 VFD_CONTROL_6: { 0 }

15
src/freedreno/registers/adreno/a6xx.xml
View file

@ -2632,12 +2632,21 @@ to upconvert to 32b float internally?
<bitfield name="REGID4VIEWID" low="24" high="31" type="a3xx_regid"/>
</reg32>
<reg32 offset="0xa002" name="VFD_CONTROL_2">
<bitfield name="REGID_HSPATCHID" low="0" high="7" type="a3xx_regid"/>
<bitfield name="REGID_HSRELPATCHID" low="0" high="7" type="a3xx_regid">
<doc>
This is the ID of the current patch within the
subdraw, used to calculate the offset of the
patch within the HS->DS buffers. When a draw is
split into multiple subdraws then this differs
from gl_PrimitiveID on the second, third, etc.
subdraws.
</doc>
</bitfield>
<bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
</reg32>
<reg32 offset="0xa003" name="VFD_CONTROL_3">
<bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/>
<bitfield name="REGID_DSPATCHID" low="8" high="15" type="a3xx_regid"/>
<bitfield name="REGID_DSPRIMID" low="0" high="7" type="a3xx_regid"/>
<bitfield name="REGID_DSRELPATCHID" low="8" high="15" type="a3xx_regid"/>
<bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
<bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
</reg32>

8
src/freedreno/vulkan/tu_pipeline.c
View file

@ -645,10 +645,10 @@ tu6_emit_vs_system_values(struct tu_cs *cs,
const uint32_t tess_coord_y_regid = VALIDREG(tess_coord_x_regid) ?
tess_coord_x_regid + 1 :
regid(63, 0);
const uint32_t hs_patch_regid = hs ?
const uint32_t hs_rel_patch_regid = hs ?
ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID) :
regid(63, 0);
const uint32_t ds_patch_regid = hs ?
const uint32_t ds_rel_patch_regid = hs ?
ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID) :
regid(63, 0);
const uint32_t hs_invocation_regid = hs ?
@ -673,9 +673,9 @@ tu6_emit_vs_system_values(struct tu_cs *cs,
A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
A6XX_VFD_CONTROL_1_REGID4VIEWID(viewid_regid));
tu_cs_emit(cs, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
tu_cs_emit(cs, A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(hs_rel_patch_regid) |
A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
tu_cs_emit(cs, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
tu_cs_emit(cs, A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(ds_rel_patch_regid) |
A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
0xfc);

16
src/gallium/drivers/freedreno/a6xx/fd6_program.c
View file

@ -320,8 +320,8 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
uint32_t stencilref_regid;
uint32_t vertex_regid, instance_regid, layer_regid, primitive_regid;
uint32_t hs_invocation_regid;
uint32_t tess_coord_x_regid, tess_coord_y_regid, hs_patch_regid,
ds_patch_regid;
uint32_t tess_coord_x_regid, tess_coord_y_regid, hs_rel_patch_regid,
ds_rel_patch_regid;
uint32_t ij_regid[IJ_COUNT];
uint32_t gs_header_regid;
enum a6xx_threadsize fssz;
@ -357,8 +357,8 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
if (hs) {
tess_coord_x_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD);
tess_coord_y_regid = next_regid(tess_coord_x_regid, 1);
hs_patch_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID);
ds_patch_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID);
hs_rel_patch_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID);
ds_rel_patch_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID);
hs_invocation_regid =
ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3);
@ -369,8 +369,8 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
} else {
tess_coord_x_regid = regid(63, 0);
tess_coord_y_regid = regid(63, 0);
hs_patch_regid = regid(63, 0);
ds_patch_regid = regid(63, 0);
hs_rel_patch_regid = regid(63, 0);
ds_rel_patch_regid = regid(63, 0);
hs_invocation_regid = regid(63, 0);
}
@ -976,9 +976,9 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
A6XX_VFD_CONTROL_1_REGID4PRIMID(primitive_regid) |
0xfc000000);
OUT_RING(ring,
A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(hs_rel_patch_regid) |
A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
OUT_RING(ring, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
OUT_RING(ring, A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(ds_rel_patch_regid) |
A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) | 0xfc);
OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */