fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-04-25 09:10:40 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 3

ac: add radeon_info::has_scratch_base_registers

Browse source 
Fixes: 3b0bfd254f - radeonsi/gfx11: make flat_scratch changes for compute

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30071>
(cherry picked from commit a5b4ae67ae)
This commit is contained in:
Marek Olšák 2024-07-12 17:45:59 -04:00 • committed by Eric Engestrom
parent 94e41cd24c
commit cd63b1d1f2
6 changed files with 9 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -1044,7 +1044,7 @@
"description": "ac: add radeon_info::has_scratch_base_registers",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "3b0bfd254f722e5773f70c6cb367e859876a4208",
"notes": null

3
src/amd/common/ac_gpu_info.c
View file

@ -1569,6 +1569,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->max_scratch_waves = MAX2(32 * info->min_good_cu_per_sa * info->max_sa_per_se * info->num_se,
max_waves_per_tg);
info->num_rb = util_bitcount64(info->enabled_rb_mask);
info->has_scratch_base_registers = info->gfx_level >= GFX11 ||
(!info->has_graphics && info->family >= CHIP_GFX940);
info->max_gflops = (info->gfx_level >= GFX11 ? 256 : 128) * info->num_cu * info->max_gpu_freq_mhz / 1000;
info->memory_bandwidth_gbps = DIV_ROUND_UP(info->memory_freq_mhz_effective * info->memory_bus_width / 8, 1000);
info->has_pcie_bandwidth_info = info->drm_minor >= 51;
@ -1978,6 +1980,7 @@ void ac_print_gpu_info(const struct radeon_info *info, FILE *f)
fprintf(f, " wave64_vgpr_alloc_granularity = %i\n", info->wave64_vgpr_alloc_granularity);
fprintf(f, " max_scratch_waves = %i\n", info->max_scratch_waves);
fprintf(f, " attribute_ring_size_per_se = %u\n", info->attribute_ring_size_per_se);
fprintf(f, " has_scratch_base_registers = %i\n", info->has_scratch_base_registers);
fprintf(f, "Render backend info:\n");
fprintf(f, " pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override);

1
src/amd/common/ac_gpu_info.h
View file

@ -264,6 +264,7 @@ struct radeon_info {
uint32_t wave64_vgpr_alloc_granularity;
uint32_t max_scratch_waves;
uint32_t attribute_ring_size_per_se;
bool has_scratch_base_registers;
/* Render backends (color + depth blocks). */
uint32_t r300_num_gb_pipes;

6
src/gallium/drivers/radeonsi/si_compute.c
View file

@ -404,7 +404,7 @@ static bool si_setup_compute_scratch_buffer(struct si_context *sctx, struct si_s
}
/* Set the scratch address in the shader binary. */
if (sctx->gfx_level < GFX11 && (sctx->family < CHIP_GFX940 || sctx->screen->info.has_graphics)) {
if (!sctx->screen->info.has_scratch_base_registers) {
uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
if (shader->scratch_va != scratch_va) {
@ -529,9 +529,7 @@ static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute
radeon_opt_set_sh_reg(sctx, R_00B860_COMPUTE_TMPRING_SIZE,
SI_TRACKED_COMPUTE_TMPRING_SIZE, sctx->compute_tmpring_size);
if (config->scratch_bytes_per_wave &&
(sctx->gfx_level >= GFX11 ||
(sctx->family >= CHIP_GFX940 && !sctx->screen->info.has_graphics))) {
if (config->scratch_bytes_per_wave && sctx->screen->info.has_scratch_base_registers) {
radeon_opt_set_sh_reg2(sctx, R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
sctx->compute_scratch_buffer->gpu_address >> 8,

3
src/gallium/drivers/radeonsi/si_shader.c
View file

@ -2955,8 +2955,7 @@ bool si_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *compi
}
/* Add/remove the scratch offset to/from input SGPRs. */
if (sel->screen->info.gfx_level < GFX11 &&
(sel->screen->info.family < CHIP_GFX940 || sel->screen->info.has_graphics) &&
if (!sel->screen->info.has_scratch_base_registers &&
!si_is_merged_shader(shader)) {
if (sscreen->use_aco) {
/* When aco scratch_offset arg is added explicitly at the beginning.

2
src/gallium/drivers/radeonsi/si_state_shaders.cpp
View file

@ -4223,7 +4223,7 @@ bool si_update_spi_tmpring_size(struct si_context *sctx, unsigned bytes)
return false;
}
if (sctx->gfx_level < GFX11 && !si_update_scratch_relocs(sctx))
if (!sctx->screen->info.has_scratch_base_registers && !si_update_scratch_relocs(sctx))
return false;
}