From ccece38623fd3dee10472ae2a68d8b8a24adcfbc Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Sat, 17 Feb 2024 15:28:18 -0800 Subject: [PATCH] intel/brw: Remove Gfx8- specific EU inst helpers The "generic" macros will be handled in a separate patch. Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_eu.h | 16 --- src/intel/compiler/brw_eu_emit.c | 169 ------------------------------ src/intel/compiler/brw_inst.h | 174 +++++++------------------------ 3 files changed, 39 insertions(+), 320 deletions(-) diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h index 7c702dcde82..d533b6a3a3c 100644 --- a/src/intel/compiler/brw_eu.h +++ b/src/intel/compiler/brw_eu.h @@ -194,10 +194,6 @@ void brw_add_reloc(struct brw_codegen *p, uint32_t id, void brw_set_dest(struct brw_codegen *p, brw_inst *insn, struct brw_reg dest); void brw_set_src0(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg); -void gfx6_resolve_implied_move(struct brw_codegen *p, - struct brw_reg *src, - unsigned msg_reg_nr); - /* Helpers for regular instructions: */ #define ALU1(OP) \ @@ -1489,14 +1485,6 @@ brw_send_indirect_split_message(struct brw_codegen *p, bool ex_bso, bool eot); -void brw_ff_sync(struct brw_codegen *p, - struct brw_reg dest, - unsigned msg_reg_nr, - struct brw_reg src0, - bool allocate, - unsigned response_length, - bool eot); - void brw_svb_write(struct brw_codegen *p, struct brw_reg dest, unsigned msg_reg_nr, @@ -1566,8 +1554,6 @@ void brw_barrier(struct brw_codegen *p, struct brw_reg src); * channel. */ brw_inst *brw_IF(struct brw_codegen *p, unsigned execute_size); -brw_inst *gfx6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional, - struct brw_reg src0, struct brw_reg src1); void brw_ELSE(struct brw_codegen *p); void brw_ENDIF(struct brw_codegen *p); @@ -1584,8 +1570,6 @@ brw_inst *brw_HALT(struct brw_codegen *p); /* Forward jumps: */ -void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx); - brw_inst *brw_JMPI(struct brw_codegen *p, struct brw_reg index, unsigned predicate_control); diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index c5ae26f67ad..76d9009cb5f 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -35,36 +35,6 @@ #include "util/ralloc.h" -/** - * Prior to Sandybridge, the SEND instruction accepted non-MRF source - * registers, implicitly moving the operand to a message register. - * - * On Sandybridge, this is no longer the case. This function performs the - * explicit move; it should be called before emitting a SEND instruction. - */ -void -gfx6_resolve_implied_move(struct brw_codegen *p, - struct brw_reg *src, - unsigned msg_reg_nr) -{ - const struct intel_device_info *devinfo = p->devinfo; - - if (src->file == BRW_MESSAGE_REGISTER_FILE) - return; - - if (src->file != BRW_ARCHITECTURE_REGISTER_FILE || src->nr != BRW_ARF_NULL) { - assert(devinfo->ver < 12); - brw_push_insn_state(p); - brw_set_default_exec_size(p, BRW_EXECUTE_8); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); - brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD), - retype(*src, BRW_REGISTER_TYPE_UD)); - brw_pop_insn_state(p); - } - *src = brw_message_reg(msg_reg_nr); -} - static void gfx7_convert_mrf_to_grf(struct brw_codegen *p, struct brw_reg *reg) { @@ -436,76 +406,6 @@ brw_set_desc_ex(struct brw_codegen *p, brw_inst *inst, brw_inst_set_send_ex_desc(devinfo, inst, ex_desc); } -static void brw_set_math_message( struct brw_codegen *p, - brw_inst *inst, - unsigned function, - unsigned integer_type, - bool low_precision, - unsigned dataType ) -{ - const struct intel_device_info *devinfo = p->devinfo; - unsigned msg_length; - unsigned response_length; - - /* Infer message length from the function */ - switch (function) { - case BRW_MATH_FUNCTION_POW: - case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT: - case BRW_MATH_FUNCTION_INT_DIV_REMAINDER: - case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER: - msg_length = 2; - break; - default: - msg_length = 1; - break; - } - - /* Infer response length from the function */ - switch (function) { - case BRW_MATH_FUNCTION_SINCOS: - case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER: - response_length = 2; - break; - default: - response_length = 1; - break; - } - - brw_set_desc(p, inst, brw_message_desc( - devinfo, msg_length, response_length, false)); - - brw_inst_set_sfid(devinfo, inst, BRW_SFID_MATH); - brw_inst_set_math_msg_function(devinfo, inst, function); - brw_inst_set_math_msg_signed_int(devinfo, inst, integer_type); - brw_inst_set_math_msg_precision(devinfo, inst, low_precision); - brw_inst_set_math_msg_saturate(devinfo, inst, brw_inst_saturate(devinfo, inst)); - brw_inst_set_math_msg_data_type(devinfo, inst, dataType); - brw_inst_set_saturate(devinfo, inst, 0); -} - - -static void brw_set_ff_sync_message(struct brw_codegen *p, - brw_inst *insn, - bool allocate, - unsigned response_length, - bool end_of_thread) -{ - const struct intel_device_info *devinfo = p->devinfo; - - brw_set_desc(p, insn, brw_message_desc( - devinfo, 1, response_length, true)); - - brw_inst_set_sfid(devinfo, insn, BRW_SFID_URB); - brw_inst_set_eot(devinfo, insn, end_of_thread); - brw_inst_set_urb_opcode(devinfo, insn, 1); /* FF_SYNC */ - brw_inst_set_urb_allocate(devinfo, insn, allocate); - /* The following fields are not used by FF_SYNC: */ - brw_inst_set_urb_global_offset(devinfo, insn, 0); - brw_inst_set_urb_swizzle_control(devinfo, insn, 0); - brw_inst_set_urb_used(devinfo, insn, 0); - brw_inst_set_urb_complete(devinfo, insn, 0); -} - static void gfx7_set_dp_scratch_message(struct brw_codegen *p, brw_inst *inst, @@ -1318,32 +1218,6 @@ brw_IF(struct brw_codegen *p, unsigned execute_size) return insn; } -/* This function is only used for gfx6-style IF instructions with an - * embedded comparison (conditional modifier). It is not used on gfx7. - */ -brw_inst * -gfx6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional, - struct brw_reg src0, struct brw_reg src1) -{ - const struct intel_device_info *devinfo = p->devinfo; - brw_inst *insn; - - insn = next_insn(p, BRW_OPCODE_IF); - - brw_set_dest(p, insn, brw_imm_w(0)); - brw_inst_set_exec_size(devinfo, insn, brw_get_default_exec_size(p)); - brw_inst_set_gfx6_jump_count(devinfo, insn, 0); - brw_set_src0(p, insn, src0); - brw_set_src1(p, insn, src1); - - assert(brw_inst_qtr_control(devinfo, insn) == BRW_COMPRESSION_NONE); - assert(brw_inst_pred_control(devinfo, insn) == BRW_PREDICATE_NONE); - brw_inst_set_cond_modifier(devinfo, insn, conditional); - - push_if_stack(p, insn); - return insn; -} - /** * Patch IF and ELSE instructions with appropriate jump targets. */ @@ -1559,25 +1433,6 @@ brw_WHILE(struct brw_codegen *p) return insn; } -/* FORWARD JUMPS: - */ -void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx) -{ - const struct intel_device_info *devinfo = p->devinfo; - brw_inst *jmp_insn = &p->store[jmp_insn_idx]; - unsigned jmpi = 2; - - assert(brw_inst_opcode(p->isa, jmp_insn) == BRW_OPCODE_JMPI); - assert(brw_inst_src1_reg_file(devinfo, jmp_insn) == BRW_IMMEDIATE_VALUE); - - brw_inst_set_gfx4_jump_count(devinfo, jmp_insn, - jmpi * (p->nr_insn - jmp_insn_idx - 1)); -} - -/* To integrate with the above, it makes sense that the comparison - * instruction should populate the flag register. It might be simpler - * just to use the flag reg for most WM tasks? - */ void brw_CMP(struct brw_codegen *p, struct brw_reg dest, unsigned conditional, @@ -2387,30 +2242,6 @@ brw_set_uip_jip(struct brw_codegen *p, int start_offset) } } -void brw_ff_sync(struct brw_codegen *p, - struct brw_reg dest, - unsigned msg_reg_nr, - struct brw_reg src0, - bool allocate, - unsigned response_length, - bool eot) -{ - brw_inst *insn; - - gfx6_resolve_implied_move(p, &src0, msg_reg_nr); - - insn = next_insn(p, BRW_OPCODE_SEND); - brw_set_dest(p, insn, dest); - brw_set_src0(p, insn, src0); - brw_set_src1(p, insn, brw_imm_d(0)); - - brw_set_ff_sync_message(p, - insn, - allocate, - response_length, - eot); -} - static unsigned brw_surface_payload_size(unsigned num_channels, unsigned exec_size /**< 0 for SIMD4x2 */) diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h index c3a324257cb..10749be5788 100644 --- a/src/intel/compiler/brw_inst.h +++ b/src/intel/compiler/brw_inst.h @@ -388,12 +388,10 @@ FF(flag_subreg_nr, F(saturate, /* 4+ */ 31, 31, /* 12+ */ 34, 34) F(debug_control, /* 4+ */ 30, 30, /* 12+ */ 30, 30) F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29) -FC(branch_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver >= 8) -FC(acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver >= 6 && devinfo->ver < 20) -FC(mask_control_ex, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->verx10 == 45 || - devinfo->ver == 5) +F(branch_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33) +FC(acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver < 20) F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ 95, 92) -FC(math_function, /* 4+ */ 27, 24, /* 12+ */ 95, 92, devinfo->ver >= 6) +F(math_function, /* 4+ */ 27, 24, /* 12+ */ 95, 92) F20(exec_size, /* 4+ */ 23, 21, /* 12+ */ 18, 16, /* 20+ */ 20, 18) F(pred_inv, /* 4+ */ 20, 20, /* 12+ */ 28, 28) F20(pred_control, /* 4+ */ 19, 16, /* 12+ */ 27, 24, /* 20+ */ 27, 26) @@ -445,12 +443,6 @@ F8(3src_a16_src1_type, /* 4+ */ -1, -1, /* 8+ */ 36, 36, /* 12+ */ -1, - F8(3src_a16_src2_type, /* 4+ */ -1, -1, /* 8+ */ 35, 35, /* 12+ */ -1, -1) F8(3src_a16_flag_reg_nr, /* 4+ */ 34, 34, /* 8+ */ 33, 33, /* 12+ */ -1, -1) F8(3src_a16_flag_subreg_nr, /* 4+ */ 33, 33, /* 8+ */ 32, 32, /* 12+ */ -1, -1) -FF(3src_a16_dst_reg_file, - /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1, - /* 6: */ 32, 32, - /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1, - /* 12: */ -1, -1, - /* 20: */ -1, -1) F(3src_saturate, /* 4+ */ 31, 31, /* 12+ */ 34, 34) F(3src_debug_control, /* 4+ */ 30, 30, /* 12+ */ 30, 30) F(3src_cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29) @@ -685,97 +677,48 @@ static inline void brw_inst_set_uip(const struct intel_device_info *devinfo, brw_inst *inst, int32_t value) { - assert(devinfo->ver >= 6); - if (devinfo->ver >= 12) brw_inst_set_src1_is_imm(devinfo, inst, 1); - if (devinfo->ver >= 8) { - brw_inst_set_bits(inst, 95, 64, (uint32_t)value); - } else { - assert(value <= (1 << 16) - 1); - assert(value > -(1 << 16)); - brw_inst_set_bits(inst, 127, 112, (uint16_t)value); - } + brw_inst_set_bits(inst, 95, 64, (uint32_t)value); } static inline int32_t brw_inst_uip(const struct intel_device_info *devinfo, const brw_inst *inst) { - assert(devinfo->ver >= 6); - - if (devinfo->ver >= 8) { - return brw_inst_bits(inst, 95, 64); - } else { - return (int16_t)brw_inst_bits(inst, 127, 112); - } + return brw_inst_bits(inst, 95, 64); } static inline void brw_inst_set_jip(const struct intel_device_info *devinfo, brw_inst *inst, int32_t value) { - assert(devinfo->ver >= 6); - if (devinfo->ver >= 12) brw_inst_set_src0_is_imm(devinfo, inst, 1); - if (devinfo->ver >= 8) { - brw_inst_set_bits(inst, 127, 96, (uint32_t)value); - } else { - assert(value <= (1 << 15) - 1); - assert(value >= -(1 << 15)); - brw_inst_set_bits(inst, 111, 96, (uint16_t)value); - } + brw_inst_set_bits(inst, 127, 96, (uint32_t)value); } static inline int32_t brw_inst_jip(const struct intel_device_info *devinfo, const brw_inst *inst) { - assert(devinfo->ver >= 6); - - if (devinfo->ver >= 8) { - return brw_inst_bits(inst, 127, 96); - } else { - return (int16_t)brw_inst_bits(inst, 111, 96); - } + return brw_inst_bits(inst, 127, 96); } - -/** Like FC, but using int16_t to handle negative jump targets. */ -#define FJ(name, high, low, assertions) \ -static inline void \ -brw_inst_set_##name(const struct intel_device_info *devinfo, brw_inst *inst, int16_t v) \ -{ \ - assert(assertions); \ - (void) devinfo; \ - brw_inst_set_bits(inst, high, low, (uint16_t) v); \ -} \ -static inline int16_t \ -brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\ -{ \ - assert(assertions); \ - (void) devinfo; \ - return brw_inst_bits(inst, high, low); \ -} - -FJ(gfx6_jump_count, 63, 48, devinfo->ver == 6) -FJ(gfx4_jump_count, 111, 96, devinfo->ver < 6) -FC(gfx4_pop_count, /* 4+ */ 115, 112, /* 12+ */ -1, -1, devinfo->ver < 6) /** @} */ /** * SEND instructions: * @{ */ -FC(send_ex_desc_ia_subreg_nr, /* 4+ */ 82, 80, /* 12+ */ 42, 40, devinfo->ver >= 9) -FC(send_src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ -1, -1, devinfo->ver >= 9) -FC(send_sel_reg32_desc, /* 4+ */ 77, 77, /* 12+ */ 48, 48, devinfo->ver >= 9) -FC(send_sel_reg32_ex_desc, /* 4+ */ 61, 61, /* 12+ */ 49, 49, devinfo->ver >= 9) +F(send_ex_desc_ia_subreg_nr, /* 4+ */ 82, 80, /* 12+ */ 42, 40) +F(send_src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ -1, -1) +F(send_sel_reg32_desc, /* 4+ */ 77, 77, /* 12+ */ 48, 48) +F(send_sel_reg32_ex_desc, /* 4+ */ 61, 61, /* 12+ */ 49, 49) F8(send_src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41, /* 12+ */ 66, 66) -FC(send_src1_reg_nr, /* 4+ */ 51, 44, /* 12+ */ 111, 104, devinfo->ver >= 9) +F(send_src1_reg_nr, /* 4+ */ 51, 44, /* 12+ */ 111, 104) FC(send_src1_len, /* 4+ */ -1, -1, /* 12+ */ 103, 99, devinfo->verx10 >= 125) -FC(send_src1_reg_file, /* 4+ */ 36, 36, /* 12+ */ 98, 98, devinfo->ver >= 9) -FC(send_dst_reg_file, /* 4+ */ 35, 35, /* 12+ */ 50, 50, devinfo->ver >= 9) +F(send_src1_reg_file, /* 4+ */ 36, 36, /* 12+ */ 98, 98) +F(send_dst_reg_file, /* 4+ */ 35, 35, /* 12+ */ 50, 50) FC(send_ex_bso, /* 4+ */ -1, -1, /* 12+ */ 39, 39, devinfo->verx10 >= 125) /** @} */ @@ -806,15 +749,9 @@ brw_inst_set_send_desc(const struct intel_device_info *devinfo, brw_inst_set_bits(inst, 55, 51, GET_BITS(value, 24, 20)); brw_inst_set_bits(inst, 121, 113, GET_BITS(value, 19, 11)); brw_inst_set_bits(inst, 91, 81, GET_BITS(value, 10, 0)); - } else if (devinfo->ver >= 9) { + } else { brw_inst_set_bits(inst, 126, 96, value); assert(value >> 31 == 0); - } else if (devinfo->ver >= 5) { - brw_inst_set_bits(inst, 124, 96, value); - assert(value >> 29 == 0); - } else { - brw_inst_set_bits(inst, 119, 96, value); - assert(value >> 24 == 0); } } @@ -833,12 +770,8 @@ brw_inst_send_desc(const struct intel_device_info *devinfo, brw_inst_bits(inst, 55, 51) << 20 | brw_inst_bits(inst, 121, 113) << 11 | brw_inst_bits(inst, 91, 81)); - } else if (devinfo->ver >= 9) { - return brw_inst_bits(inst, 126, 96); - } else if (devinfo->ver >= 5) { - return brw_inst_bits(inst, 124, 96); } else { - return brw_inst_bits(inst, 119, 96); + return brw_inst_bits(inst, 126, 96); } } @@ -999,7 +932,6 @@ FF(null_rt, /* 8: */ 80, 80, /* 12: */ 44, 44, /* 20: */ 44, 44) /* actually only Gfx11+ */ -FC(base_mrf, /* 4+ */ 27, 24, /* 12+ */ -1, -1, devinfo->ver < 6); FF(send_rta_index, /* 4: */ -1, -1, /* 4.5 */ -1, -1, @@ -1021,10 +953,7 @@ FF(urb_per_slot_offset, /* 8: */ MD(17), MD(17), /* 12: */ MD12(17), MD12(17), /* 20: */ MD12(17), MD12(17)) -FC(urb_channel_mask_present, /* 4+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15), devinfo->ver >= 8) -FC(urb_complete, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo->ver < 8) -FC(urb_used, /* 4+ */ MD(14), MD(14), /* 12+ */ -1, -1, devinfo->ver < 7) -FC(urb_allocate, /* 4+ */ MD(13), MD(13), /* 12+ */ -1, -1, devinfo->ver < 7) +F(urb_channel_mask_present, /* 4+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15)) FF(urb_swizzle_control, /* 4: */ MD(11), MD(10), /* 4.5: */ MD(11), MD(10), @@ -1053,17 +982,6 @@ FF(urb_opcode, /* 20: */ MD12(3), MD12(0)) /** @} */ -/** - * Gfx4-5 math messages: - * @{ - */ -FC(math_msg_data_type, /* 4+ */ MD(7), MD(7), /* 12+ */ -1, -1, devinfo->ver < 6) -FC(math_msg_saturate, /* 4+ */ MD(6), MD(6), /* 12+ */ -1, -1, devinfo->ver < 6) -FC(math_msg_precision, /* 4+ */ MD(5), MD(5), /* 12+ */ -1, -1, devinfo->ver < 6) -FC(math_msg_signed_int, /* 4+ */ MD(4), MD(4), /* 12+ */ -1, -1, devinfo->ver < 6) -FC(math_msg_function, /* 4+ */ MD(3), MD(0), /* 12+ */ -1, -1, devinfo->ver < 6) -/** @} */ - /** * Sampler message function control bits: * @{ @@ -1085,7 +1003,6 @@ FF(sampler_msg_type, /* 8: */ MD(16), MD(12), /* 12: */ MD12(16), MD12(12), /* 20: */ MD12(16), MD12(12)) -FC(sampler_return_format, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo->verx10 == 40) FD(sampler, /* 4: */ MD(11), MD(8), /* 4.5: */ MD(11), MD(8), @@ -1101,7 +1018,7 @@ F(binding_table_index, /* 4+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0)) /* * Data port message function control bits: * @{ */ -FC(dp_category, /* 4+ */ MD(18), MD(18), /* 12+ */ MD12(18), MD12(18), devinfo->ver >= 7) +F(dp_category, /* 4+ */ MD(18), MD(18), /* 12+ */ MD12(18), MD12(18)) /* Gfx4-5 store fields in different bits for read/write messages. */ FF(dp_read_msg_type, @@ -1138,16 +1055,6 @@ FD(dp_write_msg_control, /* 7: */ MD(13), MD( 8), /* 8: */ MD(13), MD( 8), /* 12: */ MD12(13), MD12(11), MD12(10), MD12(8)) -FC(dp_read_target_cache, /* 4+ */ MD(15), MD(14), /* 12+ */ -1, -1, devinfo->ver < 6); - -FF(dp_write_commit, - /* 4: */ MD(15), MD(15), - /* 4.5: */ MD(15), MD(15), - /* 5: */ MD(15), MD(15), - /* 6: */ MD(17), MD(17), - /* 7+: does not exist */ -1, -1, -1, -1, - /* 12: */ -1, -1, - /* 20: */ -1, -1) /* Gfx6+ use the same bit locations for everything. */ FF(dp_msg_type, @@ -1168,13 +1075,13 @@ FD(dp_msg_control, /** @} */ /** - * Scratch message bits (Gfx7+): + * Scratch message bits: * @{ */ -FC(scratch_read_write, /* 4+ */ MD(17), MD(17), /* 12+ */ MD12(17), MD12(17), devinfo->ver >= 7) /* 0 = read, 1 = write */ -FC(scratch_type, /* 4+ */ MD(16), MD(16), /* 12+ */ -1, -1, devinfo->ver >= 7) /* 0 = OWord, 1 = DWord */ -FC(scratch_invalidate_after_read, /* 4+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15), devinfo->ver >= 7) -FC(scratch_block_size, /* 4+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12), devinfo->ver >= 7) +F(scratch_read_write, /* 4+ */ MD(17), MD(17), /* 12+ */ MD12(17), MD12(17)) /* 0 = read, 1 = write */ +F(scratch_type, /* 4+ */ MD(16), MD(16), /* 12+ */ -1, -1) /* 0 = OWord, 1 = DWord */ +F(scratch_invalidate_after_read, /* 4+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15)) +F(scratch_block_size, /* 4+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12)) FD(scratch_addr_offset, /* 4: */ -1, -1, /* 4.5: */ -1, -1, @@ -1198,7 +1105,7 @@ FF(rt_last, /* 8: */ MD(12), MD(12), /* 12: */ MD12(12), MD12(12), /* 20: */ MD12(12), MD12(12)) -FC(rt_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11), devinfo->ver >= 6) +F(rt_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11)) F(rt_message_type, /* 4+ */ MD(10), MD( 8), /* 12+ */ MD12(10), MD12(8)) /** @} */ @@ -1248,7 +1155,6 @@ brw_inst_imm_uq(const struct intel_device_info *devinfo, return brw_inst_bits(insn, 95, 64) << 32 | brw_inst_bits(insn, 127, 96); } else { - assert(devinfo->ver >= 8); return brw_inst_bits(insn, 127, 64); } } @@ -1660,10 +1566,8 @@ F20(dst_reg_nr, /* 4+ */ 47, 40, /* 8+ */ 47, 40, /* 12+ */ 23, 16, /* 20+ F(src1_index, /* 4+ */ 39, 35, /* 12+ */ 55, 52) F20(src0_index, /* 4+ */ 34, 30, /* 8+ */ 34, 30, /* 12+ */ 51, 48, /* 20+ */ 25, 23) F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29) /* Same location as brw_inst */ -FC(flag_subreg_nr, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->ver <= 6) F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ -1, -1) /* Same location as brw_inst */ -FC(acc_wr_control, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->ver >= 6) -FC(mask_control_ex, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->verx10 == 45 || devinfo->ver == 5) +F(acc_wr_control, /* 4+ */ 23, 23, /* 12+ */ -1, -1) F20(subreg_index, /* 4+ */ 22, 18, /* 8+ */ 22, 18, /* 12+ */ 39, 35, /* 20+ */ 51, 48) FD20(datatype_index, /* 4+ */ 17, 13, /* 8+ */ 17, 13, /* 12+ */ 34, 30, /* 20+ */ 28, 26, 31, 30) F20(control_index, /* 4+ */ 12, 8, /* 8+ */ 12, 8, /* 12+ */ 28, 24, /* 20+ */ 22, 18) @@ -1684,21 +1588,21 @@ brw_compact_inst_imm(const struct intel_device_info *devinfo, } /** - * (Gfx8+) Compacted three-source instructions: + * Compacted three-source instructions: * @{ */ -FC(3src_src2_reg_nr, /* 4+ */ 63, 57, /* 12+ */ 55, 48, devinfo->ver >= 8) -FC(3src_src1_reg_nr, /* 4+ */ 56, 50, /* 12+ */ 63, 56, devinfo->ver >= 8) -FC(3src_src0_reg_nr, /* 4+ */ 49, 43, /* 12+ */ 47, 40, devinfo->ver >= 8) -FC(3src_src2_subreg_nr, /* 4+ */ 42, 40, /* 12+ */ -1, -1, devinfo->ver >= 8) -FC(3src_src1_subreg_nr, /* 4+ */ 39, 37, /* 12+ */ -1, -1, devinfo->ver >= 8) -FC(3src_src0_subreg_nr, /* 4+ */ 36, 34, /* 12+ */ -1, -1, devinfo->ver >= 8) -FC(3src_src2_rep_ctrl, /* 4+ */ 33, 33, /* 12+ */ -1, -1, devinfo->ver >= 8) -FC(3src_src1_rep_ctrl, /* 4+ */ 32, 32, /* 12+ */ -1, -1, devinfo->ver >= 8) -FC(3src_saturate, /* 4+ */ 31, 31, /* 12+ */ -1, -1, devinfo->ver >= 8) -FC(3src_debug_control, /* 4+ */ 30, 30, /* 12+ */ 7, 7, devinfo->ver >= 8) -FC(3src_cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29, devinfo->ver >= 8) -FC(3src_src0_rep_ctrl, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->ver >= 8) +F(3src_src2_reg_nr, /* 4+ */ 63, 57, /* 12+ */ 55, 48) +F(3src_src1_reg_nr, /* 4+ */ 56, 50, /* 12+ */ 63, 56) +F(3src_src0_reg_nr, /* 4+ */ 49, 43, /* 12+ */ 47, 40) +F(3src_src2_subreg_nr, /* 4+ */ 42, 40, /* 12+ */ -1, -1) +F(3src_src1_subreg_nr, /* 4+ */ 39, 37, /* 12+ */ -1, -1) +F(3src_src0_subreg_nr, /* 4+ */ 36, 34, /* 12+ */ -1, -1) +F(3src_src2_rep_ctrl, /* 4+ */ 33, 33, /* 12+ */ -1, -1) +F(3src_src1_rep_ctrl, /* 4+ */ 32, 32, /* 12+ */ -1, -1) +F(3src_saturate, /* 4+ */ 31, 31, /* 12+ */ -1, -1) +F(3src_debug_control, /* 4+ */ 30, 30, /* 12+ */ 7, 7) +F(3src_cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29) +F(3src_src0_rep_ctrl, /* 4+ */ 28, 28, /* 12+ */ -1, -1) /* Reserved */ F20(3src_dst_reg_nr, /* 4+ */ 18, 12, /* 8+ */ 18, 12, /* 12+ */ 23, 16, /* 20+ */ 39, 32) F20(3src_source_index, /* 4+ */ -1, -1, /* 8+ */ 11, 10, /* 12+ */ 34, 30, /* 20+ */ 25, 22) @@ -1706,7 +1610,7 @@ FD20(3src_subreg_index, /* 4+ */ -1, -1, /* 8+ */ -1, -1, /* 12+ */ 39, 35, /* F20(3src_control_index, /* 4+ */ -1, -1, /* 8+ */ 9, 8, /* 12+ */ 28, 24, /* 20+ */ 21, 18) F20(3src_swsb, /* 4+ */ -1, -1, /* 8+ */ -1, -1, /* 12+ */ 15, 8, /* 20+ */ 17, 8) /* Bit 7 is Reserved (for future Opcode expansion) */ -FC(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0, devinfo->ver >= 8) +F(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0) /** @} */ #undef F