radeonsi: adjust flags for si_compute_shorten_ubyte_buffer

- no need to flush anything before as we're working on a clean
  buffer (SI_OP_SKIP_CACHE_INV_BEFORE)
- L2 must be flushed after the job to avoid rendering artifacts.
  Instead of setting it manually, use SI_OP_SYNC_AFTER +
  SI_COHERENCY_NONE.

Fixes: 1a99f50c7f ("radeonsi: use a compute shader to convert unsupported indices format")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27095>

src/gallium/drivers/radeonsi/si_compute_blit.c

@@ -535,7 +535,10 @@ void si_compute_shorten_ubyte_buffer(struct si_context *sctx, struct pipe_resour
    if (!sctx->cs_ubyte_to_ushort)
       sctx->cs_ubyte_to_ushort = si_create_ubyte_to_ushort_compute_shader(sctx);
 
-   enum si_coherency coher = SI_COHERENCY_SHADER;
+   /* Use COHERENCY_NONE to get SI_CONTEXT_WB_L2 automatically used in
+    * si_launch_grid_internal_ssbos.
+    */
+   enum si_coherency coher = SI_COHERENCY_NONE;
 
    si_improve_sync_flags(sctx, dst, src, &flags);
 

src/gallium/drivers/radeonsi/si_state_draw.cpp

@@ -2049,7 +2049,7 @@ static void si_draw(struct pipe_context *ctx,
 
          si_compute_shorten_ubyte_buffer(sctx, indexbuf, info->index.resource,
                                          start_offset, index_offset + start, count,
-                                         SI_OP_SYNC_AFTER);
+                                         SI_OP_SKIP_CACHE_INV_BEFORE | SI_OP_SYNC_AFTER);
 
          index_offset = 0;
          index_size = 2;