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ac/gpu_info: fix more non-coherent RB and GL2 combinations

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It ignored non-harvested chips with a non-power-of-two memory bus.

Fixes: abed921ce7 - amd: add support for Navy Flounder

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10170>
This commit is contained in:
Marek Olšák 2021-03-12 10:26:54 -05:00 • committed by Pierre-Eric Pelloux-Prayer
parent 3877a9ec99
commit ccc4abdbf4
4 changed files with 9 additions and 7 deletions
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8
src/amd/common/ac_gpu_info.c
View file

@ -698,16 +698,18 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->tcc_cache_line_size = 128;
if (info->drm_minor >= 35) {
info->tcc_harvested = device_info.tcc_disabled_mask != 0;
info->num_tcc_blocks = info->max_tcc_blocks - util_bitcount64(device_info.tcc_disabled_mask);
} else {
/* This is a hack, but it's all we can do without a kernel upgrade. */
info->tcc_harvested = (info->vram_size / info->max_tcc_blocks) != 512 * 1024 * 1024;
info->num_tcc_blocks = info->vram_size / (512 * 1024 * 1024);
if (info->num_tcc_blocks > info->max_tcc_blocks)
info->num_tcc_blocks /= 2;
}
} else {
info->tcc_cache_line_size = 64;
info->num_tcc_blocks = info->max_tcc_blocks;
}
info->mc_arb_ramcfg = amdinfo->mc_arb_ramcfg;
info->gb_addr_config = amdinfo->gb_addr_cfg;
if (info->chip_class >= GFX9) {
@ -1063,7 +1065,7 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
fprintf(f, " max_tcc_blocks = %i\n", info->max_tcc_blocks);
fprintf(f, " num_tcc_blocks = %i\n", info->num_tcc_blocks);
fprintf(f, " tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
fprintf(f, " tcc_harvested = %u\n", info->tcc_harvested);
fprintf(f, " tcc_rb_non_coherent = %u\n", info->tcc_rb_non_coherent);
fprintf(f, " pc_lines = %u\n", info->pc_lines);
fprintf(f, " lds_size_per_workgroup = %u\n", info->lds_size_per_workgroup);
fprintf(f, " lds_granularity = %i\n", info->lds_granularity);

2
src/amd/common/ac_gpu_info.h
View file

@ -106,7 +106,7 @@ struct radeon_info {
uint32_t max_tcc_blocks;
uint32_t num_tcc_blocks;
uint32_t tcc_cache_line_size;
bool tcc_harvested;
bool tcc_rb_non_coherent; /* whether L2 inv is needed for render->texture transitions */
unsigned pc_lines;
uint32_t lds_size_per_workgroup;
uint32_t lds_granularity;

2
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -3316,7 +3316,7 @@ static bool
radv_image_is_l2_coherent(const struct radv_device *device, const struct radv_image *image)
{
if (device->physical_device->rad_info.chip_class >= GFX10) {
return !device->physical_device->rad_info.tcc_harvested &&
return !device->physical_device->rad_info.tcc_rb_non_coherent &&
(image && !radv_image_is_pipe_misaligned(device, image));
} else if (device->physical_device->rad_info.chip_class == GFX9 && image) {
if (image->info.samples == 1 &&

4
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -1744,7 +1744,7 @@ static inline void si_make_CB_shader_coherent(struct si_context *sctx, unsigned
sctx->force_cb_shader_coherent = false;
if (sctx->chip_class >= GFX10) {
if (sctx->screen->info.tcc_harvested)
if (sctx->screen->info.tcc_rb_non_coherent)
sctx->flags |= SI_CONTEXT_INV_L2;
else if (shaders_read_metadata)
sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
@ -1769,7 +1769,7 @@ static inline void si_make_DB_shader_coherent(struct si_context *sctx, unsigned
sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_INV_VCACHE;
if (sctx->chip_class >= GFX10) {
if (sctx->screen->info.tcc_harvested)
if (sctx->screen->info.tcc_rb_non_coherent)
sctx->flags |= SI_CONTEXT_INV_L2;
else if (shaders_read_metadata)
sctx->flags |= SI_CONTEXT_INV_L2_METADATA;