diff --git a/src/amd/common/ac_uvd_dec.h b/src/amd/common/ac_uvd_dec.h
index 826d1d1bc3a..94cf8a9a0cc 100644
--- a/src/amd/common/ac_uvd_dec.h
+++ b/src/amd/common/ac_uvd_dec.h
@@ -383,7 +383,7 @@ struct ruvd_msg {
          uint32_t dt_uv_surf_tile_config;
          // re-use dt_wa_chroma_top_offset as dt_ext_info for UV pitch in stoney
          uint32_t dt_wa_chroma_top_offset;
-         uint32_t dt_wa_chroma_bottom_offset;
+         uint32_t dt_wa_chroma_bottom_offset; /* gfx9: used as dt_swizzle_mode */
 
          uint32_t reserved[16];
 
diff --git a/src/gallium/drivers/radeonsi/radeon_uvd.c b/src/gallium/drivers/radeonsi/radeon_uvd.c
index e7932cd2916..3764e9c492f 100644
--- a/src/gallium/drivers/radeonsi/radeon_uvd.c
+++ b/src/gallium/drivers/radeonsi/radeon_uvd.c
@@ -1493,9 +1493,7 @@ void si_uvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
       break;
    case RUVD_SURFACE_TYPE_GFX9:
       msg->body.decode.dt_pitch = luma->u.gfx9.surf_pitch * luma->blk_w;
-      /* SWIZZLE LINEAR MODE */
-      msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
-      msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR;
+      msg->body.decode.dt_wa_chroma_bottom_offset = luma->u.gfx9.swizzle_mode;
       msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0, type);
       msg->body.decode.dt_chroma_top_offset = texture_offset(chroma, 0, type);
       if (msg->body.decode.dt_field_mode) {