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freedreno/ir3: refactor/simplify cp
If we handle separately the special case of eliminating output mov (which includes keeps and various other cases where we don't have a consuming instruction's src register to collapse things into), we can simplify the logic. Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
parent
680664dff9
commit
cc7ed34df9
1 changed files with 83 additions and 88 deletions
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@ -41,16 +41,22 @@ static bool is_eligible_mov(struct ir3_instruction *instr, bool allow_flags)
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struct ir3_register *dst = instr->regs[0];
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struct ir3_register *src = instr->regs[1];
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struct ir3_instruction *src_instr = ssa(src);
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/* only if mov src is SSA (not const/immed): */
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if (!src_instr)
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return false;
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/* no indirect: */
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if (dst->flags & IR3_REG_RELATIV)
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return false;
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if (src->flags & IR3_REG_RELATIV)
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return false;
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if (!allow_flags)
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if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
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IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
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return false;
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if (!src_instr)
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return false;
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/* TODO: remove this hack: */
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if (is_meta(src_instr) && (src_instr->opc == OPC_META_FO))
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return false;
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@ -82,10 +88,17 @@ static bool valid_flags(struct ir3_instruction *instr, unsigned n,
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unsigned valid_flags;
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flags = cp_flags(flags);
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/* If destination is indirect, then source cannot be.. at least
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* I don't think so..
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*/
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if ((instr->regs[0]->flags & IR3_REG_RELATIV) &&
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(flags & IR3_REG_RELATIV))
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return false;
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/* clear flags that are 'ok' */
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switch (instr->category) {
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case 1:
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valid_flags = IR3_REG_IMMED | IR3_REG_RELATIV;
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valid_flags = IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV;
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if (flags & ~valid_flags)
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return false;
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break;
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@ -183,9 +196,13 @@ static void combine_flags(unsigned *dstflags, unsigned srcflags)
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*dstflags ^= IR3_REG_SNEG;
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if (srcflags & IR3_REG_BNOT)
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*dstflags ^= IR3_REG_BNOT;
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}
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static struct ir3_instruction * instr_cp(struct ir3_instruction *instr, unsigned *flags);
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*dstflags &= ~IR3_REG_SSA;
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*dstflags |= srcflags & IR3_REG_SSA;
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*dstflags |= srcflags & IR3_REG_CONST;
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*dstflags |= srcflags & IR3_REG_IMMED;
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*dstflags |= srcflags & IR3_REG_RELATIV;
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}
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/* the "plain" MAD's (ie. the ones that don't shift first src prior to
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* multiply) can swap their first two srcs if src[0] is !CONST and
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@ -206,52 +223,31 @@ static bool is_valid_mad(struct ir3_instruction *instr)
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static void
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reg_cp(struct ir3_instruction *instr, struct ir3_register *reg, unsigned n)
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{
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unsigned src_flags = 0, new_flags;
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struct ir3_instruction *src_instr;
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struct ir3_instruction *src = ssa(reg);
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if (is_meta(instr)) {
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/* meta instructions cannot fold up register
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* flags.. they are usually src for texture
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* fetch, etc, where we cannot specify abs/neg
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*/
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reg->instr = instr_cp(reg->instr, NULL);
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return;
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}
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if (is_eligible_mov(src, true)) {
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/* simple case, no immed/const/relativ, only mov's w/ ssa src: */
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struct ir3_register *src_reg = src->regs[1];
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unsigned new_flags = reg->flags;
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src_instr = instr_cp(reg->instr, &src_flags);
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combine_flags(&new_flags, src_reg->flags);
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new_flags = reg->flags;
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combine_flags(&new_flags, src_flags);
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reg->flags = new_flags;
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reg->instr = src_instr;
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if (!valid_flags(instr, n, reg->flags)) {
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/* insert an absneg.f */
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if (reg->flags & (IR3_REG_SNEG | IR3_REG_SABS | IR3_REG_BNOT)) {
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debug_assert(!(reg->flags & (IR3_REG_FNEG | IR3_REG_FABS)));
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reg->instr = ir3_ABSNEG_S(instr->block,
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reg->instr, cp_flags(src_flags));
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} else {
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debug_assert(!(reg->flags & (IR3_REG_SNEG | IR3_REG_SABS | IR3_REG_BNOT)));
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reg->instr = ir3_ABSNEG_F(instr->block,
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reg->instr, cp_flags(src_flags));
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if (valid_flags(instr, n, new_flags)) {
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reg->flags = new_flags;
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reg->instr = ssa(src_reg);
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}
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reg->flags &= ~cp_flags(src_flags);
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debug_assert(valid_flags(instr, n, reg->flags));
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/* send it through instr_cp() again since
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* the absneg src might be a mov from const
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* that could be cleaned up:
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*/
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reg->instr = instr_cp(reg->instr, NULL);
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return;
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}
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if (is_same_type_mov(reg->instr)) {
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struct ir3_register *src_reg = reg->instr->regs[1];
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unsigned new_flags = src_reg->flags;
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src = ssa(reg); /* could be null for IR3_REG_ARRAY case */
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if (!src)
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return;
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} else if (is_same_type_mov(src) &&
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/* cannot collapse const/immed/etc into meta instrs: */
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!is_meta(instr)) {
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/* immed/const/etc cases, which require some special handling: */
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struct ir3_register *src_reg = src->regs[1];
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unsigned new_flags = reg->flags;
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combine_flags(&new_flags, reg->flags);
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combine_flags(&new_flags, src_reg->flags);
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if (!valid_flags(instr, n, new_flags)) {
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/* special case for "normal" mad instructions, we can
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@ -330,7 +326,8 @@ reg_cp(struct ir3_instruction *instr, struct ir3_register *reg, unsigned n)
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if (new_flags & IR3_REG_BNOT)
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iim_val = ~iim_val;
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if (!(iim_val & ~0x3ff)) {
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/* other than category 1 (mov) we can only encode up to 10 bits: */
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if ((instr->category == 1) || !(iim_val & ~0x3ff)) {
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new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
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src_reg->flags = new_flags;
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src_reg->iim_val = iim_val;
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@ -342,56 +339,53 @@ reg_cp(struct ir3_instruction *instr, struct ir3_register *reg, unsigned n)
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}
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}
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/**
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* Given an SSA src (instruction), return the one with extraneous
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* mov's removed, ie, for (to copy NIR syntax):
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*
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* vec1 ssa1 = fadd <something>, <somethingelse>
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* vec1 ssa2 = fabs ssa1
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* vec1 ssa3 = fneg ssa1
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*
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* then calling instr_cp(ssa3, &flags) would return ssa1 with
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* (IR3_REG_ABS | IR3_REG_NEGATE) in flags. If flags is NULL,
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* then disallow eliminating copies which would require flag
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* propagation (for example, we cannot propagate abs/neg into
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* an output).
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/* Handle special case of eliminating output mov, and similar cases where
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* there isn't a normal "consuming" instruction. In this case we cannot
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* collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
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* be eliminated)
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*/
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static struct ir3_instruction *
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instr_cp(struct ir3_instruction *instr, unsigned *flags)
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eliminate_output_mov(struct ir3_instruction *instr)
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{
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if (is_eligible_mov(instr, false)) {
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struct ir3_register *reg = instr->regs[1];
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struct ir3_instruction *src_instr = ssa(reg);
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debug_assert(src_instr);
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return src_instr;
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}
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return instr;
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}
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/**
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* Find instruction src's which are mov's that can be collapsed, replacing
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* the mov dst with the mov src
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*/
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static void
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instr_cp(struct ir3_instruction *instr)
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{
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struct ir3_register *reg;
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if (is_eligible_mov(instr, !!flags)) {
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struct ir3_register *reg = instr->regs[1];
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struct ir3_instruction *src_instr = ssa(reg);
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if (flags)
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combine_flags(flags, reg->flags);
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return instr_cp(src_instr, flags);
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}
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if (instr->regs_count == 0)
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return;
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/* Check termination condition before walking children (rather
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* than before checking eligible-mov). A mov instruction may
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* appear as ssa-src for multiple other instructions, and we
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* want to consider it for removal for each, rather than just
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* the first one. (But regardless of how many places it shows
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* up as a src, we only need to recursively walk the children
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* once.)
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*/
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if (ir3_instr_check_mark(instr))
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return instr;
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return;
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/* walk down the graph from each src: */
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foreach_src_n(reg, n, instr) {
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if (!(reg->flags & IR3_REG_SSA))
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struct ir3_instruction *src = ssa(reg);
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if (!src)
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continue;
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instr_cp(src);
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reg_cp(instr, reg, n);
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}
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if (instr->address)
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ir3_instr_set_address(instr, instr_cp(instr->address, NULL));
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return instr;
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if (instr->address) {
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instr_cp(instr->address);
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ir3_instr_set_address(instr, eliminate_output_mov(instr->address));
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}
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}
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void
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@ -401,19 +395,20 @@ ir3_cp(struct ir3 *ir)
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for (unsigned i = 0; i < ir->noutputs; i++) {
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if (ir->outputs[i]) {
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struct ir3_instruction *out =
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instr_cp(ir->outputs[i], NULL);
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ir->outputs[i] = out;
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instr_cp(ir->outputs[i]);
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ir->outputs[i] = eliminate_output_mov(ir->outputs[i]);
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}
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}
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for (unsigned i = 0; i < ir->keeps_count; i++) {
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ir->keeps[i] = instr_cp(ir->keeps[i], NULL);
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instr_cp(ir->keeps[i]);
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ir->keeps[i] = eliminate_output_mov(ir->keeps[i]);
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}
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list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
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if (block->condition)
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block->condition = instr_cp(block->condition, NULL);
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if (block->condition) {
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instr_cp(block->condition);
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block->condition = eliminate_output_mov(block->condition);
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}
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}
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}
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