diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index d7296f3dc2b..8ea4ca49c8b 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -10502,7 +10502,7 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, const struct radv
          uint64_t indirect_va = info->va;
          const bool needs_align32_workaround = pdev->info.has_async_compute_align32_bug &&
                                                cmd_buffer->qf == RADV_QUEUE_COMPUTE &&
-                                               !radv_is_aligned(indirect_va, 32);
+                                               !util_is_aligned(indirect_va, 32);
          const unsigned ace_predication_size =
             4 /* DISPATCH_INDIRECT */ + (needs_align32_workaround ? 6 * 3 /* 3x COPY_DATA */ : 0);
 
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 777f6c6ef6c..b99e894ce50 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -124,14 +124,6 @@ extern "C" {
 #define CLOCK_MONOTONIC_RAW CLOCK_MONOTONIC_FAST
 #endif
 
-/** Alignment must be a power of 2. */
-static inline bool
-radv_is_aligned(uintmax_t n, uintmax_t a)
-{
-   assert(a == (a & -a));
-   return (n & (a - 1)) == 0;
-}
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c
index c889adc203f..28412c1d78c 100644
--- a/src/amd/vulkan/radv_queue.c
+++ b/src/amd/vulkan/radv_queue.c
@@ -603,7 +603,7 @@ radv_emit_task_rings(struct radv_device *device, struct radeon_cmdbuf *cs, struc
       return;
 
    const uint64_t task_ctrlbuf_va = radv_buffer_get_va(task_rings_bo);
-   assert(radv_is_aligned(task_ctrlbuf_va, 256));
+   assert(util_is_aligned(task_ctrlbuf_va, 256));
    radv_cs_add_buffer(device->ws, cs, task_rings_bo);
 
    /* Tell the GPU where the task control buffer is. */
diff --git a/src/amd/vulkan/radv_sdma.c b/src/amd/vulkan/radv_sdma.c
index e1e049c9ddb..0b6e07eb8c7 100644
--- a/src/amd/vulkan/radv_sdma.c
+++ b/src/amd/vulkan/radv_sdma.c
@@ -72,13 +72,13 @@ radv_sdma_check_pitches(const unsigned pitch, const unsigned slice_pitch, const
    ASSERTED const unsigned pitch_alignment = MAX2(1, 4 / bpp);
    assert(pitch);
    assert(pitch <= (1 << 14));
-   assert(radv_is_aligned(pitch, pitch_alignment));
+   assert(util_is_aligned(pitch, pitch_alignment));
 
    if (uses_depth) {
       ASSERTED const unsigned slice_pitch_alignment = 4;
       assert(slice_pitch);
       assert(slice_pitch <= (1 << 28));
-      assert(radv_is_aligned(slice_pitch, slice_pitch_alignment));
+      assert(util_is_aligned(slice_pitch, slice_pitch_alignment));
    }
 }
 
@@ -597,13 +597,13 @@ radv_sdma_use_unaligned_buffer_image_copy(const struct radv_device *device, cons
                                           const struct radv_sdma_surf *img, const VkExtent3D ext)
 {
    const unsigned pitch_blocks = radv_sdma_pixels_to_blocks(buf->pitch, img->blk_w);
-   if (!radv_is_aligned(pitch_blocks, radv_sdma_pitch_alignment(device, img->bpp)))
+   if (!util_is_aligned(pitch_blocks, radv_sdma_pitch_alignment(device, img->bpp)))
       return true;
 
    const bool uses_depth = img->offset.z != 0 || ext.depth != 1;
    if (!img->is_linear && uses_depth) {
       const unsigned slice_pitch_blocks = radv_sdma_pixel_area_to_blocks(buf->slice_pitch, img->blk_w, img->blk_h);
-      if (!radv_is_aligned(slice_pitch_blocks, 4))
+      if (!util_is_aligned(slice_pitch_blocks, 4))
          return true;
    }
 
@@ -742,17 +742,17 @@ radv_sdma_use_t2t_scanline_copy(const struct radv_device *device, const struct r
    const VkOffset3D src_offset_blk = radv_sdma_pixel_offset_to_blocks(src->offset, src->blk_w, src->blk_h);
    const VkOffset3D dst_offset_blk = radv_sdma_pixel_offset_to_blocks(dst->offset, dst->blk_w, dst->blk_h);
 
-   if (!radv_is_aligned(copy_extent_blk.width, alignment->width) ||
-       !radv_is_aligned(copy_extent_blk.height, alignment->height) ||
-       !radv_is_aligned(copy_extent_blk.depth, alignment->depth))
+   if (!util_is_aligned(copy_extent_blk.width, alignment->width) ||
+       !util_is_aligned(copy_extent_blk.height, alignment->height) ||
+       !util_is_aligned(copy_extent_blk.depth, alignment->depth))
       return true;
 
-   if (!radv_is_aligned(src_offset_blk.x, alignment->width) || !radv_is_aligned(src_offset_blk.y, alignment->height) ||
-       !radv_is_aligned(src_offset_blk.z, alignment->depth))
+   if (!util_is_aligned(src_offset_blk.x, alignment->width) || !util_is_aligned(src_offset_blk.y, alignment->height) ||
+       !util_is_aligned(src_offset_blk.z, alignment->depth))
       return true;
 
-   if (!radv_is_aligned(dst_offset_blk.x, alignment->width) || !radv_is_aligned(dst_offset_blk.y, alignment->height) ||
-       !radv_is_aligned(dst_offset_blk.z, alignment->depth))
+   if (!util_is_aligned(dst_offset_blk.x, alignment->width) || !util_is_aligned(dst_offset_blk.y, alignment->height) ||
+       !util_is_aligned(dst_offset_blk.z, alignment->depth))
       return true;
 
    return false;