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intel/genxml: add PIPE_CONTROL command cache invalidate bit

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This new bit invalidates the cache/prefetch of commands in the command
streamer. This will be useful for self modifying batches.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
This commit is contained in:
Lionel Landwerlin 2020-02-02 14:25:16 +01:00
parent 34a0ce58c7
commit cc13bfbd05
2 changed files with 2 additions and 0 deletions
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1
src/intel/genxml/gen11.xml
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@ -6272,6 +6272,7 @@
<value name="GGTT" value="1"/>
</field>
<field name="Flush LLC" start="58" end="58" type="bool"/>
<field name="Command Cache Invalidate Enable" start="61" end="61" type="bool"/>
<field name="Address" start="66" end="111" type="address"/>
<field name="Immediate Data" start="128" end="191" type="uint"/>
</instruction>

1
src/intel/genxml/gen12.xml
View file

@ -6413,6 +6413,7 @@
</field>
<field name="Flush LLC" start="58" end="58" type="bool"/>
<field name="Tile Cache Flush Enable" start="60" end="60" type="bool"/>
<field name="Command Cache Invalidate Enable" start="61" end="61" type="bool"/>
<field name="Address" start="66" end="111" type="address"/>
<field name="Immediate Data" start="128" end="191" type="uint"/>
</instruction>