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i965: Enable fast clears on non-8x4-aligned sizes.

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Improves glb2.7 performance at a misaligned size by 2.3% +/- 0.7% (n=11).
The workaround was to avoid bad primitive/surface sizes, but that's worked
around as of a14dc4f92c.  (One might note
that pre-gen7 we don't know that the right half of an 8x4 at the right
edge is actually our pixels, but we're already clobbering those pixels for
depth resolves anyway and more work would be required to avoid that).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
This commit is contained in:
Eric Anholt 2013-04-23 13:58:31 -07:00
parent 76084907fb
commit cbf3462c35
1 changed files with 0 additions and 13 deletions
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13
src/mesa/drivers/dri/i965/brw_clear.c
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@ -128,19 +128,6 @@ brw_fast_clear_depth(struct gl_context *ctx)
return false;
}
/* The rendered area has to be 8x4 samples, not resolved pixels, so we look
* at the miptree slice dimensions instead of renderbuffer size.
*/
if (mt->level[depth_irb->mt_level].width % 8 != 0 ||
mt->level[depth_irb->mt_level].height % 4 != 0) {
perf_debug("Failed to fast clear depth due to width/height %d,%d not "
"being aligned to 8,4. Possible 5%% performance win if "
"avoided\n",
mt->level[depth_irb->mt_level].width,
mt->level[depth_irb->mt_level].height);
return false;
}
uint32_t depth_clear_value;
switch (mt->format) {
case MESA_FORMAT_Z32_FLOAT_X24S8: