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iris: Add read-write domain for data cache.

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This will allow us to remove the history flushes performed for SSBOs
and instead take advantage of the same mechanism used for tracking
other memory accesses.

v2: Use C99 designated initializers (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12691>
This commit is contained in:
Francisco Jerez 2020-05-29 17:22:55 -07:00 • committed by Marge Bot
parent c677e76483
commit cb9f02f863
3 changed files with 10 additions and 0 deletions
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2
src/gallium/drivers/iris/iris_bufmgr.h
View file

@ -105,6 +105,8 @@ enum iris_domain {
IRIS_DOMAIN_RENDER_WRITE = 0,
/** (Hi)Z/stencil cache. */
IRIS_DOMAIN_DEPTH_WRITE,
/** Data port (HDC) cache. */
IRIS_DOMAIN_DATA_WRITE,
/** Any other read-write cache. */
IRIS_DOMAIN_OTHER_WRITE,
/** Vertex cache. */

2
src/gallium/drivers/iris/iris_pipe_control.c
View file

@ -190,6 +190,7 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch,
const uint32_t flush_bits[NUM_IRIS_DOMAINS] = {
[IRIS_DOMAIN_RENDER_WRITE] = PIPE_CONTROL_RENDER_TARGET_FLUSH,
[IRIS_DOMAIN_DEPTH_WRITE] = PIPE_CONTROL_DEPTH_CACHE_FLUSH,
[IRIS_DOMAIN_DATA_WRITE] = PIPE_CONTROL_DATA_CACHE_FLUSH,
[IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE,
[IRIS_DOMAIN_VF_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD,
[IRIS_DOMAIN_OTHER_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD,
@ -197,6 +198,7 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch,
const uint32_t invalidate_bits[NUM_IRIS_DOMAINS] = {
[IRIS_DOMAIN_RENDER_WRITE] = PIPE_CONTROL_RENDER_TARGET_FLUSH,
[IRIS_DOMAIN_DEPTH_WRITE] = PIPE_CONTROL_DEPTH_CACHE_FLUSH,
[IRIS_DOMAIN_DATA_WRITE] = PIPE_CONTROL_DATA_CACHE_FLUSH,
[IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE,
[IRIS_DOMAIN_VF_READ] = PIPE_CONTROL_VF_CACHE_INVALIDATE,
[IRIS_DOMAIN_OTHER_READ] = (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |

6
src/gallium/drivers/iris/iris_state.c
View file

@ -7380,6 +7380,9 @@ batch_mark_sync_for_pipe_control(struct iris_batch *batch, uint32_t flags)
if ((flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH))
iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_DEPTH_WRITE);
if ((flags & PIPE_CONTROL_DATA_CACHE_FLUSH))
iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_DATA_WRITE);
if ((flags & PIPE_CONTROL_FLUSH_ENABLE))
iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_OTHER_WRITE);
@ -7396,6 +7399,9 @@ batch_mark_sync_for_pipe_control(struct iris_batch *batch, uint32_t flags)
if ((flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH))
iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_DEPTH_WRITE);
if ((flags & PIPE_CONTROL_DATA_CACHE_FLUSH))
iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_DATA_WRITE);
if ((flags & PIPE_CONTROL_FLUSH_ENABLE))
iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_OTHER_WRITE);