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radeonsi/gfx10: implement a GE bug workaround

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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
This commit is contained in:
Marek Olšák 2019-07-30 18:33:01 -04:00
parent e08b0d7ac4
commit cb9d95623b
1 changed files with 18 additions and 0 deletions
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18
src/gallium/drivers/radeonsi/si_state_shaders.c
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@ -1230,6 +1230,24 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) | S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi); S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
/* Bug workaround for a possible hang with non-tessellation cases.
* Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
*
* Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
*/
if ((sscreen->info.family == CHIP_NAVI10 ||
sscreen->info.family == CHIP_NAVI12 ||
sscreen->info.family == CHIP_NAVI14) &&
(es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
shader->ngg.hw_max_esverts != 256) {
shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
if (shader->ngg.hw_max_esverts > 5) {
shader->ge_cntl |=
S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
}
}
if (window_space) { if (window_space) {
shader->ctx_reg.ngg.pa_cl_vte_cntl = shader->ctx_reg.ngg.pa_cl_vte_cntl =
S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1); S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);