diff --git a/src/amd/vpelib/inc/vpe_hw_types.h b/src/amd/vpelib/inc/vpe_hw_types.h index 3d476ea22c1..1ccb3219901 100644 --- a/src/amd/vpelib/inc/vpe_hw_types.h +++ b/src/amd/vpelib/inc/vpe_hw_types.h @@ -97,9 +97,10 @@ enum vpe_mirror { }; enum vpe_scan_direction { - VPE_SCAN_DIRECTION_UNKNOWN = 0, - VPE_SCAN_DIRECTION_HORIZONTAL = 1, /* 0, 180 rotation */ - VPE_SCAN_DIRECTION_VERTICAL = 2, /* 90, 270 rotation */ + VPE_SCAN_PATTERN_0_DEGREE = 0, + VPE_SCAN_PATTERN_90_DEGREE = 1, + VPE_SCAN_PATTERN_180_DEGREE = 2, + VPE_SCAN_PATTERN_270_DEGREE = 3, }; struct vpe_size { diff --git a/src/amd/vpelib/inc/vpe_types.h b/src/amd/vpelib/inc/vpe_types.h index f97179d1518..350dcc49e55 100644 --- a/src/amd/vpelib/inc/vpe_types.h +++ b/src/amd/vpelib/inc/vpe_types.h @@ -195,6 +195,7 @@ struct vpe_dcc_surface_param { enum vpe_surface_pixel_format format; enum vpe_swizzle_mode_values swizzle_mode; enum vpe_scan_direction scan; + enum vpe_mirror mirror; }; struct vpe_dcc_setting { diff --git a/src/amd/vpelib/meson.build b/src/amd/vpelib/meson.build index ae2c2ee03d1..e6de3cdde18 100644 --- a/src/amd/vpelib/meson.build +++ b/src/amd/vpelib/meson.build @@ -63,7 +63,6 @@ vpe_files = files( 'src/core/vpe_visual_confirm.c', 'src/core/mpc.c', 'src/core/config_writer.c', - 'src/core/plane_desc_writer.c', 'src/core/color_gamut.c', 'src/core/vpelib.c', 'src/core/vpe_desc_writer.c', @@ -85,6 +84,9 @@ vpe_files = files( 'src/utils/custom_float.c', 'src/utils/conversion.c', 'src/utils/fixpt31_32.c', + 'src/chip/vpe10/inc/vpe10_command.h', + 'src/chip/vpe10/inc/vpe10_plane_desc_writer.h', + 'src/chip/vpe10/vpe10_plane_desc_writer.c', 'src/chip/vpe10/inc/vpe10_background.h', 'src/chip/vpe10/inc/vpe10_cm_common.h', 'src/chip/vpe10/inc/vpe10_vpec.h', diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_command.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_command.h new file mode 100644 index 00000000000..65cabcaa34a --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_command.h @@ -0,0 +1,137 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once +#include "vpe_command.h" + +#ifdef __cplusplus +extern "C" { +#endif +/*************************** + * VPE Descriptor + ***************************/ +#define VPE_DESC_CD__SHIFT 16 +#define VPE_DESC_CD_MASK 0x000F0000 + +#define VPE_DESC_ADDR__SHIFT 32 +#define VPE_DESC_HIGH_ADDR_MASK 0xFFFFFFFF00000000 + +/* The lowest bits are reuse and tmz as bit 1 and bit 0. + Smibs will substract the address with emb gpuva to + get offset and then reuse bit will be preserved + So as long as the embedded buffer is allocated + at correct alignment (currently low addr is [31:2] + which means we need a 4 byte(2 bit) alignment), + the offset generated will still cover the + reuse bit as part of it. + Ex : Address : 0x200036 GPU Virtual Address : 0x200000 + offset is 0x36 which keeps the reuse bit */ +#define VPE_DESC_LOW_ADDR_MASK 0x00000000FFFFFFFF +#define VPE_DESC_REUSE_TMZ_MASK 0x0000000000000003 + +#define VPE_DESC_NUM_CONFIG_DESCRIPTOR__SHIFT 0 +#define VPE_DESC_NUM_CONFIG_DESCRIPTOR_MASK 0x000000FF + +#define VPE_DESC_REUSE__MASK 0x00000002 + +#define VPE_DESC_CMD_HEADER(cd) \ + (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPE_DESC, 0) | (((cd) << VPE_DESC_CD__SHIFT) & VPE_DESC_CD_MASK)) + +/*************************** + * VPE Plane Config + ***************************/ +enum VPE_PLANE_CFG_SUBOP { + VPE_PLANE_CFG_SUBOP_1_TO_1 = 0x0, + VPE_PLANE_CFG_SUBOP_2_TO_1 = 0x1, + VPE_PLANE_CFG_SUBOP_2_TO_2 = 0x2 +}; + +#define VPE_PLANE_CFG_ONE_PLANE 0 +#define VPE_PLANE_CFG_TWO_PLANES 1 + +#define VPE_PLANE_CFG_NPS0__SHIFT 16 +#define VPE_PLANE_CFG_NPS0_MASK 0x00030000 + +#define VPE_PLANE_CFG_NPD0__SHIFT 18 +#define VPE_PLANE_CFG_NPD0_MASK 0x000C0000 + +#define VPE_PLANE_CFG_NPS1__SHIFT 20 +#define VPE_PLANE_CFG_NPS1_MASK 0x00300000 + +#define VPE_PLANE_CFG_NPD1__SHIFT 22 +#define VPE_PLANE_CFG_NPD1_MASK 0x00C00000 + +#define VPE_PLANE_CFG_TMZ__SHIFT 16 +#define VPE_PLANE_CFG_TMZ_MASK 0x00010000 + +#define VPE_PLANE_CFG_SWIZZLE_MODE__SHIFT 3 +#define VPE_PLANE_CFG_SWIZZLE_MODE_MASK 0x000000F8 + +#define VPE_PLANE_CFG_ROTATION__SHIFT 0 +#define VPE_PLANE_CFG_ROTATION_MASK 0x00000003 + +#define VPE_PLANE_CFG_MIRROR__SHIFT 0 +#define VPE_PLANE_CFG_MIRROR_MASK 0x00000003 + +#define VPE_PLANE_ADDR_LO__SHIFT 0 +#define VPE_PLANE_ADDR_LO_MASK 0xFFFFFF00 + +#define VPE_PLANE_CFG_PITCH__SHIFT 0 +#define VPE_PLANE_CFG_PITCH_MASK 0x00003FFF + +#define VPE_PLANE_CFG_VIEWPORT_Y__SHIFT 16 +#define VPE_PLANE_CFG_VIEWPORT_Y_MASK 0x3FFF0000 +#define VPE_PLANE_CFG_VIEWPORT_X__SHIFT 0 +#define VPE_PLANE_CFG_VIEWPORT_X_MASK 0x00003FFF + +#define VPE_PLANE_CFG_VIEWPORT_HEIGHT__SHIFT 16 +#define VPE_PLANE_CFG_VIEWPORT_HEIGHT_MASK 0x1FFF0000 +#define VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE__SHIFT 13 +#define VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE_MASK 0x0000E000 +#define VPE_PLANE_CFG_VIEWPORT_WIDTH__SHIFT 0 +#define VPE_PLANE_CFG_VIEWPORT_WIDTH_MASK 0x00001FFF + +#define VPE_PLANE_ADDR__SHIFT 32 +#define VPE_PLANE_HIGH_ADDR_MASK 0xFFFFFFFF00000000 + +#define VPE_PLANE_LOW_ADDR_MASK 0x00000000FFFFFFFF +#define VPE_PLANE_REUSE_TMZ_MASK 0x0000000000000003 + +enum VPE_PLANE_CFG_ELEMENT_SIZE { + VPE_PLANE_CFG_ELEMENT_SIZE_8BPE = 0, + VPE_PLANE_CFG_ELEMENT_SIZE_16BPE = 1, + VPE_PLANE_CFG_ELEMENT_SIZE_32BPE = 2, + VPE_PLANE_CFG_ELEMENT_SIZE_64BPE = 3 +}; + +#define VPE_PLANE_CFG_CMD_HEADER(subop, nps0, npd0, nps1, npd1) \ + (VPE_CMD_HEADER(VPE_CMD_OPCODE_PLANE_CFG, subop) | \ + (((nps0) << VPE_PLANE_CFG_NPS0__SHIFT) & VPE_PLANE_CFG_NPS0_MASK) | \ + (((npd0) << VPE_PLANE_CFG_NPD0__SHIFT) & VPE_PLANE_CFG_NPD0_MASK) | \ + (((nps1) << VPE_PLANE_CFG_NPS1__SHIFT) & VPE_PLANE_CFG_NPS1_MASK) | \ + (((npd0) << VPE_PLANE_CFG_NPD1__SHIFT) & VPE_PLANE_CFG_NPD1_MASK)) + + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_plane_desc_writer.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_plane_desc_writer.h new file mode 100644 index 00000000000..6c2b1415f57 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_plane_desc_writer.h @@ -0,0 +1,57 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "vpe_types.h" +#include "plane_desc_writer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** initialize the plane descriptor writer. + * Calls right before building any plane descriptor + * + * /param writer writer instance + * /param buf points to the current buf, + * /param plane_desc_header header + */ + +void vpe10_plane_desc_writer_init( + struct plane_desc_writer *writer, struct vpe_buf *buf, struct plane_desc_header *header); + +/** fill the value to the embedded buffer. */ +void vpe10_plane_desc_writer_add_source( + struct plane_desc_writer *writer, struct plane_desc_src *source, bool is_plane0); + +/** fill the value to the embedded buffer. */ +void vpe10_plane_desc_writer_add_destination( + struct plane_desc_writer *writer, struct plane_desc_dst *destination, bool is_plane0); + +void vpe10_construct_plane_desc_writer(struct plane_desc_writer *writer); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_cmd_builder.c b/src/amd/vpelib/src/chip/vpe10/vpe10_cmd_builder.c index 438c4dff4b0..90a8d638a72 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_cmd_builder.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_cmd_builder.c @@ -7,6 +7,7 @@ * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * + * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * @@ -24,14 +25,12 @@ #include "vpe_assert.h" #include "common.h" #include "vpe_priv.h" -#include "vpe_command.h" +#include "vpe10_command.h" #include "vpe10_cmd_builder.h" -#include "plane_desc_writer.h" #include "reg_helper.h" /***** Internal helpers *****/ -static void get_np(struct vpe_priv *vpe_priv, struct vpe_cmd_info *cmd_info, int32_t *nps0, - int32_t *nps1, int32_t *npd0, int32_t *npd1); +static void get_np_and_subop(struct vpe_priv *vpe_priv, struct vpe_cmd_info *cmd_info, struct plane_desc_header *header); static enum VPE_PLANE_CFG_ELEMENT_SIZE vpe_get_element_size( enum vpe_surface_pixel_format format, int plane_idx); @@ -169,23 +168,23 @@ enum vpe_status vpe10_build_plane_descriptor( { struct stream_ctx *stream_ctx; struct vpe_surface_info *surface_info; - int32_t nps0, nps1, npd0, npd1; int32_t stream_idx; struct vpe_cmd_info *cmd_info; PHYSICAL_ADDRESS_LOC *addrloc; struct plane_desc_src src; struct plane_desc_dst dst; + struct plane_desc_header header = {0}; + struct cmd_builder *builder = &vpe_priv->resource.cmd_builder; + struct plane_desc_writer *plane_desc_writer = &vpe_priv->plane_desc_writer; cmd_info = &vpe_priv->vpe_cmd_info[cmd_idx]; VPE_ASSERT(cmd_info->num_inputs == 1); // obtains number of planes for each source/destination stream - get_np(vpe_priv, cmd_info, &nps0, &nps1, &npd0, &npd1); - - plane_desc_writer_init( - &vpe_priv->plane_desc_writer, buf, nps0, npd0, nps1, npd1, VPE_PLANE_CFG_SUBOP_1_TO_1); + get_np_and_subop(vpe_priv, cmd_info, &header); + plane_desc_writer->init(&vpe_priv->plane_desc_writer, buf, &header); stream_idx = cmd_info->inputs[0].stream_idx; stream_ctx = &vpe_priv->stream_ctx[stream_idx]; surface_info = &stream_ctx->stream.surface_info; @@ -206,7 +205,7 @@ enum vpe_status vpe10_build_plane_descriptor( src.viewport_h = (uint16_t)cmd_info->inputs[0].scaler_data.viewport.height; src.elem_size = (uint8_t)(vpe_get_element_size(surface_info->format, 0)); - plane_desc_writer_add_source(&vpe_priv->plane_desc_writer, &src, true); + plane_desc_writer->add_source(&vpe_priv->plane_desc_writer, &src, true); if (vpe_is_dual_plane_format(surface_info->format)) { addrloc = &surface_info->address.video_progressive.chroma_addr; @@ -220,7 +219,7 @@ enum vpe_status vpe10_build_plane_descriptor( src.viewport_h = (uint16_t)cmd_info->inputs[0].scaler_data.viewport_c.height; src.elem_size = (uint8_t)(vpe_get_element_size(surface_info->format, 1)); - plane_desc_writer_add_source(&vpe_priv->plane_desc_writer, &src, false); + plane_desc_writer->add_source(&vpe_priv->plane_desc_writer, &src, false); } } else { addrloc = &surface_info->address.grph.addr; @@ -234,7 +233,7 @@ enum vpe_status vpe10_build_plane_descriptor( src.viewport_h = (uint16_t)cmd_info->inputs[0].scaler_data.viewport.height; src.elem_size = (uint8_t)(vpe_get_element_size(surface_info->format, 0)); - plane_desc_writer_add_source(&vpe_priv->plane_desc_writer, &src, true); + plane_desc_writer->add_source(&vpe_priv->plane_desc_writer, &src, true); } surface_info = &vpe_priv->output_ctx.surface; @@ -254,52 +253,54 @@ enum vpe_status vpe10_build_plane_descriptor( dst.base_addr_lo = addrloc->u.low_part; dst.base_addr_hi = (uint32_t)addrloc->u.high_part; dst.pitch = (uint16_t)surface_info->plane_size.surface_pitch; - dst.viewport_x = (uint16_t)cmd_info->dst_viewport.x; - dst.viewport_y = (uint16_t)cmd_info->dst_viewport.y; - dst.viewport_w = (uint16_t)cmd_info->dst_viewport.width; - dst.viewport_h = (uint16_t)cmd_info->dst_viewport.height; + dst.viewport_x = (uint16_t)cmd_info->outputs[0].dst_viewport.x; + dst.viewport_y = (uint16_t)cmd_info->outputs[0].dst_viewport.y; + dst.viewport_w = (uint16_t)cmd_info->outputs[0].dst_viewport.width; + dst.viewport_h = (uint16_t)cmd_info->outputs[0].dst_viewport.height; dst.elem_size = (uint8_t)(vpe_get_element_size(surface_info->format, 0)); - plane_desc_writer_add_destination(&vpe_priv->plane_desc_writer, &dst, true); + plane_desc_writer->add_destination(&vpe_priv->plane_desc_writer, &dst, true); return vpe_priv->plane_desc_writer.status; } -static void get_np(struct vpe_priv *vpe_priv, struct vpe_cmd_info *cmd_info, int32_t *nps0, - int32_t *nps1, int32_t *npd0, int32_t *npd1) +static void get_np_and_subop(struct vpe_priv *vpe_priv, struct vpe_cmd_info *cmd_info, + struct plane_desc_header *header) { - *npd1 = 0; + header->npd1 = 0; + + header->subop = VPE_PLANE_CFG_SUBOP_1_TO_1; if (cmd_info->num_inputs == 1) { - *nps1 = 0; + header->nps1 = 0; if (vpe_is_dual_plane_format( vpe_priv->stream_ctx[cmd_info->inputs[0].stream_idx].stream.surface_info.format)) - *nps0 = VPE_PLANE_CFG_TWO_PLANES; + header->nps0 = VPE_PLANE_CFG_TWO_PLANES; else - *nps0 = VPE_PLANE_CFG_ONE_PLANE; + header->nps0 = VPE_PLANE_CFG_ONE_PLANE; } else if (cmd_info->num_inputs == 2) { if (vpe_is_dual_plane_format( vpe_priv->stream_ctx[cmd_info->inputs[0].stream_idx].stream.surface_info.format)) - *nps0 = VPE_PLANE_CFG_TWO_PLANES; + header->nps0 = VPE_PLANE_CFG_TWO_PLANES; else - *nps0 = VPE_PLANE_CFG_ONE_PLANE; + header->nps0 = VPE_PLANE_CFG_ONE_PLANE; if (vpe_is_dual_plane_format( vpe_priv->stream_ctx[cmd_info->inputs[1].stream_idx].stream.surface_info.format)) - *nps1 = VPE_PLANE_CFG_TWO_PLANES; + header->nps1 = VPE_PLANE_CFG_TWO_PLANES; else - *nps1 = VPE_PLANE_CFG_ONE_PLANE; + header->nps1 = VPE_PLANE_CFG_ONE_PLANE; } else { - *nps0 = 0; - *nps1 = 0; - *npd0 = 0; + header->nps0 = 0; + header->nps1 = 0; + header->npd0 = 0; return; } if (vpe_is_dual_plane_format(vpe_priv->output_ctx.surface.format)) - *npd0 = 1; + header->npd0 = 1; else - *npd0 = 0; + header->npd0 = 0; } static enum VPE_PLANE_CFG_ELEMENT_SIZE vpe_get_element_size( diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_opp.c b/src/amd/vpelib/src/chip/vpe10/vpe10_opp.c index d8f92c0e5f2..70d430e5ffd 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_opp.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_opp.c @@ -26,7 +26,7 @@ #include "common.h" #include "vpe_priv.h" #include "vpe10_opp.h" -#include "vpe_command.h" +#include "vpe10_command.h" #include "hw_shared.h" #include "reg_helper.h" diff --git a/src/amd/vpelib/src/core/plane_desc_writer.c b/src/amd/vpelib/src/chip/vpe10/vpe10_plane_desc_writer.c similarity index 88% rename from src/amd/vpelib/src/core/plane_desc_writer.c rename to src/amd/vpelib/src/chip/vpe10/vpe10_plane_desc_writer.c index d7e4dfc5fae..64425bd2e34 100644 --- a/src/amd/vpelib/src/core/plane_desc_writer.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_plane_desc_writer.c @@ -23,12 +23,19 @@ */ #include "vpe_assert.h" -#include "vpe_command.h" -#include "plane_desc_writer.h" +#include "vpe10_command.h" +#include "vpe10_plane_desc_writer.h" #include "reg_helper.h" -void plane_desc_writer_init(struct plane_desc_writer *writer, struct vpe_buf *buf, int32_t nps0, - int32_t npd0, int32_t nps1, int32_t npd1, int32_t subop) +void vpe10_construct_plane_desc_writer(struct plane_desc_writer *writer) +{ + writer->init = vpe10_plane_desc_writer_init; + writer->add_source = vpe10_plane_desc_writer_add_source; + writer->add_destination = vpe10_plane_desc_writer_add_destination; +} + +void vpe10_plane_desc_writer_init( + struct plane_desc_writer *writer, struct vpe_buf *buf, struct plane_desc_header *header) { uint32_t *cmd_space; uint64_t size = 4; @@ -46,7 +53,8 @@ void plane_desc_writer_init(struct plane_desc_writer *writer, struct vpe_buf *bu } cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; - *cmd_space++ = VPE_PLANE_CFG_CMD_HEADER(subop, nps0, npd0, nps1, npd1); + *cmd_space++ = VPE_PLANE_CFG_CMD_HEADER( + header->subop, header->nps0, header->npd0, header->nps1, header->npd1); writer->buf->cpu_va += size; writer->buf->gpu_va += size; @@ -54,7 +62,7 @@ void plane_desc_writer_init(struct plane_desc_writer *writer, struct vpe_buf *bu } /** fill the value to the embedded buffer. */ -void plane_desc_writer_add_source( +void vpe10_plane_desc_writer_add_source( struct plane_desc_writer *writer, struct plane_desc_src *src, bool is_plane0) { uint32_t *cmd_space, *cmd_start; @@ -98,7 +106,7 @@ void plane_desc_writer_add_source( } /** fill the value to the embedded buffer. */ -void plane_desc_writer_add_destination( +void vpe10_plane_desc_writer_add_destination( struct plane_desc_writer *writer, struct plane_desc_dst *dst, bool is_plane0) { uint32_t *cmd_space, *cmd_start; diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c b/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c index d2f01a6ea3b..682f3cd83cd 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c @@ -31,9 +31,10 @@ #include "vpe10_dpp.h" #include "vpe10_mpc.h" #include "vpe10_opp.h" -#include "vpe_command.h" +#include "vpe10_command.h" #include "vpe10_cm_common.h" #include "vpe10_background.h" +#include "vpe10_plane_desc_writer.h" #include "vpe10/inc/asic/bringup_vpe_6_1_0_offset.h" #include "vpe10/inc/asic/bringup_vpe_6_1_0_sh_mask.h" #include "vpe10/inc/asic/bringup_vpe_6_1_0_default.h" @@ -358,6 +359,7 @@ enum vpe_status vpe10_construct_resource(struct vpe_priv *vpe_priv, struct resou if (!res->opp[0]) goto err; + vpe10_construct_plane_desc_writer(&vpe_priv->plane_desc_writer); vpe10_construct_cmd_builder(vpe_priv, &res->cmd_builder); vpe_priv->num_pipe = 1; @@ -885,8 +887,9 @@ enum vpe_status vpe10_populate_cmd_info(struct vpe_priv *vpe_priv) cmd_info->cd = (uint8_t)(stream_ctx->num_segments - segment_idx - 1); memcpy(&(cmd_info->inputs[0].scaler_data), &(stream_ctx->segment_ctx[segment_idx].scaler_data), sizeof(struct scaler_data)); - cmd_info->dst_viewport = stream_ctx->segment_ctx[segment_idx].scaler_data.dst_viewport; - cmd_info->dst_viewport_c = + cmd_info->num_outputs = 1; + cmd_info->outputs[0].dst_viewport = stream_ctx->segment_ctx[segment_idx].scaler_data.dst_viewport; + cmd_info->outputs[0].dst_viewport_c = stream_ctx->segment_ctx[segment_idx].scaler_data.dst_viewport_c; cmd_info->num_inputs = 1; cmd_info->ops = VPE_CMD_OPS_COMPOSITING; diff --git a/src/amd/vpelib/src/chip/vpe11/inc/vpe11_cmd_builder.h b/src/amd/vpelib/src/chip/vpe11/inc/vpe11_cmd_builder.h index 5d19287df7e..76be05b82a3 100644 --- a/src/amd/vpelib/src/chip/vpe11/inc/vpe11_cmd_builder.h +++ b/src/amd/vpelib/src/chip/vpe11/inc/vpe11_cmd_builder.h @@ -24,6 +24,7 @@ #pragma once #include "cmd_builder.h" +#include "vpe11_command.h" #ifdef __cplusplus extern "C" { diff --git a/src/amd/vpelib/src/chip/vpe11/inc/vpe11_command.h b/src/amd/vpelib/src/chip/vpe11/inc/vpe11_command.h new file mode 100644 index 00000000000..d3ec6c31551 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe11/inc/vpe11_command.h @@ -0,0 +1,49 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once +#include "vpe10_command.h" + +#ifdef __cplusplus + extern "C" { +#endif + +#undef VPE_DESC_CD__SHIFT +#undef VPE_DESC_CD_MASK +#undef VPE_DESC_CMD_HEADER + +#define VPE_DESC_CD__SHIFT 16 +#define VPE_DESC_CD_MASK 0x001F0000 + +#define VPE_DESC_CMD_HEADER(cd) \ + (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPE_DESC, 0) | (((cd) << VPE_DESC_CD__SHIFT) & VPE_DESC_CD_MASK)) + + // Collaborate sync Command Header +#define VPE_COLLABORATE_SYNC_HEADER_MASK 0x000000FF +#define VPE_COLLABORATE_SYNC_DATA_MASK(collaborate_data) ((collaborate_data) & 0xFFFFFFFF) +#define VPE_COLLABORATE_SYNC_CMD_HEADER \ + (VPE_CMD_HEADER(VPE_CMD_OPCODE_COLLABORATE_SYNC, 0) & VPE_COLLABORATE_SYNC_HEADER_MASK) + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe11/vpe11_cmd_builder.c b/src/amd/vpelib/src/chip/vpe11/vpe11_cmd_builder.c index 4321bf5b10d..9827e2627a8 100644 --- a/src/amd/vpelib/src/chip/vpe11/vpe11_cmd_builder.c +++ b/src/amd/vpelib/src/chip/vpe11/vpe11_cmd_builder.c @@ -24,18 +24,16 @@ #include "vpe_assert.h" #include "common.h" #include "vpe_priv.h" -#include "vpe_command.h" +#include "vpe11_command.h" #include "vpe10_cmd_builder.h" #include "vpe11_cmd_builder.h" -#include "plane_desc_writer.h" #include "reg_helper.h" void vpe11_construct_cmd_builder(struct vpe_priv *vpe_priv, struct cmd_builder *builder) { - builder->build_noops = vpe10_build_noops; - builder->build_vpe_cmd = vpe10_build_vpe_cmd; - builder->build_plane_descriptor = vpe10_build_plane_descriptor; - // build collaborate sync cmd + builder->build_noops = vpe10_build_noops; + builder->build_vpe_cmd = vpe10_build_vpe_cmd; + builder->build_plane_descriptor = vpe10_build_plane_descriptor; builder->build_collaborate_sync_cmd = vpe11_build_collaborate_sync_cmd; } diff --git a/src/amd/vpelib/src/chip/vpe11/vpe11_resource.c b/src/amd/vpelib/src/chip/vpe11/vpe11_resource.c index 8e5d1c9a5a2..b95c6b5e940 100644 --- a/src/amd/vpelib/src/chip/vpe11/vpe11_resource.c +++ b/src/amd/vpelib/src/chip/vpe11/vpe11_resource.c @@ -32,9 +32,10 @@ #include "vpe10_dpp.h" #include "vpe10_mpc.h" #include "vpe10_opp.h" -#include "vpe_command.h" +#include "vpe11_command.h" #include "vpe10_cm_common.h" #include "vpe10_background.h" +#include "vpe10_plane_desc_writer.h" #include "vpe10/inc/asic/bringup_vpe_6_1_0_offset.h" #include "vpe10/inc/asic/bringup_vpe_6_1_0_sh_mask.h" #include "vpe10/inc/asic/bringup_vpe_6_1_0_default.h" @@ -165,6 +166,7 @@ enum vpe_status vpe11_construct_resource(struct vpe_priv *vpe_priv, struct resou if (!res->opp[0]) goto err; + vpe10_construct_plane_desc_writer(&vpe_priv->plane_desc_writer); vpe11_construct_cmd_builder(vpe_priv, &res->cmd_builder); vpe_priv->num_pipe = 1; diff --git a/src/amd/vpelib/src/core/background.c b/src/amd/vpelib/src/core/background.c index bdf092fd1e8..a0aae14b8f2 100644 --- a/src/amd/vpelib/src/core/background.c +++ b/src/amd/vpelib/src/core/background.c @@ -110,14 +110,14 @@ void vpe_create_bg_segments( VPE_ASSERT(gaps_cnt - gap_index - 1 <= (uint16_t)0xF); // background takes stream_idx 0 as its input - vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].inputs[0].stream_idx = 0; - vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].dst_viewport = scaler_data->dst_viewport; - vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].dst_viewport_c = scaler_data->dst_viewport_c; - vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].num_inputs = 1; - vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].ops = ops; - vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].cd = (uint8_t)(gaps_cnt - gap_index - 1); - vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].tm_enabled = - false; // currently only support frontend tm + vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].inputs[0].stream_idx = 0; + vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].num_outputs = 1; + vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].outputs[0].dst_viewport = scaler_data->dst_viewport; + vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].outputs[0].dst_viewport_c = scaler_data->dst_viewport_c; + vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].num_inputs = 1; + vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].ops = ops; + vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].cd = (uint8_t)(gaps_cnt - gap_index - 1); + vpe_priv->vpe_cmd_info[vpe_priv->num_vpe_cmds].tm_enabled = false; // currently only support frontend tm vpe_priv->num_vpe_cmds++; } diff --git a/src/amd/vpelib/src/core/common.c b/src/amd/vpelib/src/core/common.c index 5e48b0af6d7..1322f2ed99e 100644 --- a/src/amd/vpelib/src/core/common.c +++ b/src/amd/vpelib/src/core/common.c @@ -390,12 +390,12 @@ enum vpe_status vpe_check_output_support(struct vpe *vpe, const struct vpe_build // output dcc if (surface_info->dcc.enable) { + params.surface_size.width = surface_info->plane_size.surface_size.width; params.surface_size.height = surface_info->plane_size.surface_size.height; params.format = surface_info->format; params.swizzle_mode = surface_info->swizzle; - params.scan = VPE_SCAN_DIRECTION_HORIZONTAL; - + params.scan = VPE_SCAN_PATTERN_0_DEGREE; support = vpe->cap_funcs->get_dcc_compression_output_cap(vpe, ¶ms, &cap); if (!support) { vpe_log("output dcc not supported\n"); @@ -498,14 +498,6 @@ enum vpe_status vpe_check_input_support(struct vpe *vpe, const struct vpe_stream params.format = surface_info->format; params.swizzle_mode = surface_info->swizzle; - if (stream->rotation == VPE_ROTATION_ANGLE_0 || stream->rotation == VPE_ROTATION_ANGLE_180) - params.scan = VPE_SCAN_DIRECTION_HORIZONTAL; - else if (stream->rotation == VPE_ROTATION_ANGLE_90 || - stream->rotation == VPE_ROTATION_ANGLE_270) - params.scan = VPE_SCAN_DIRECTION_VERTICAL; - else - params.scan = VPE_SCAN_DIRECTION_UNKNOWN; - support = vpe->cap_funcs->get_dcc_compression_input_cap(vpe, ¶ms, &cap); //only support non dual plane formats if (!support) { diff --git a/src/amd/vpelib/src/core/config_writer.c b/src/amd/vpelib/src/core/config_writer.c index 5a9c8fd2552..cd10df2b2e3 100644 --- a/src/amd/vpelib/src/core/config_writer.c +++ b/src/amd/vpelib/src/core/config_writer.c @@ -23,7 +23,6 @@ */ #include "vpe_assert.h" -#include "vpe_command.h" #include "config_writer.h" #include "reg_helper.h" #include "common.h" diff --git a/src/amd/vpelib/src/core/inc/cmd_builder.h b/src/amd/vpelib/src/core/inc/cmd_builder.h index 0c0a7938ad6..aed03d850be 100644 --- a/src/amd/vpelib/src/core/inc/cmd_builder.h +++ b/src/amd/vpelib/src/core/inc/cmd_builder.h @@ -25,6 +25,7 @@ #pragma once #include "vpe_types.h" +#include "plane_desc_writer.h" #ifdef __cplusplus extern "C" { diff --git a/src/amd/vpelib/src/core/inc/plane_desc_writer.h b/src/amd/vpelib/src/core/inc/plane_desc_writer.h index a289b247bdc..b57da8132c8 100644 --- a/src/amd/vpelib/src/core/inc/plane_desc_writer.h +++ b/src/amd/vpelib/src/core/inc/plane_desc_writer.h @@ -25,24 +25,15 @@ #pragma once #include "vpe_types.h" - #ifdef __cplusplus extern "C" { #endif - -struct plane_desc_writer { - struct vpe_buf *buf; /**< store the current buf pointer */ - - /* store the base addr of the currnet config - * i.e. config header - * it is always constructed in emb_buf - */ - uint64_t base_gpu_va; - uint64_t base_cpu_va; - - int32_t num_src; - int32_t num_dst; - enum vpe_status status; +struct plane_desc_header { + int32_t nps0; + int32_t npd0; + int32_t nps1; + int32_t npd1; + int32_t subop; }; struct plane_desc_src { @@ -73,28 +64,29 @@ struct plane_desc_dst { uint8_t elem_size; }; -/** initialize the plane descriptor writer. - * Calls right before building any plane descriptor - * - * /param writer writer instance - * /param buf points to the current buf, - * each config_writer_fill will update the address - * /param nps0 number of plane for source 0 - * /param npd0 number of plane for desination 0 - * /param nps1 number of plane for source 1 - * /param npd1 number of plane for desination 1 - * /param subop subop code - */ -void plane_desc_writer_init(struct plane_desc_writer *writer, struct vpe_buf *buf, int32_t nps0, - int32_t npd0, int32_t nps1, int32_t npd1, int32_t subop); -/** fill the value to the embedded buffer. */ -void plane_desc_writer_add_source( - struct plane_desc_writer *writer, struct plane_desc_src *source, bool is_plane0); +struct plane_desc_writer { + struct vpe_buf *buf; /**< store the current buf pointer */ -/** fill the value to the embedded buffer. */ -void plane_desc_writer_add_destination( - struct plane_desc_writer *writer, struct plane_desc_dst *destination, bool is_plane0); + /* store the base addr of the currnet config + * i.e. config header + * it is always constructed in emb_buf + */ + uint64_t base_gpu_va; + uint64_t base_cpu_va; + + int32_t num_src; + int32_t num_dst; + enum vpe_status status; + + void (*init)( + struct plane_desc_writer *writer, struct vpe_buf *buf, struct plane_desc_header *header); + void (*add_source)( + struct plane_desc_writer *writer, struct plane_desc_src *source, bool is_plane0); + void (*add_destination)( + struct plane_desc_writer *writer, struct plane_desc_dst *destination, bool is_plane0); + void (*add_meta)(struct plane_desc_writer *writer, struct plane_desc_src *src); +}; #ifdef __cplusplus } diff --git a/src/amd/vpelib/src/core/inc/reg_helper.h b/src/amd/vpelib/src/core/inc/reg_helper.h index da4641add5c..036affed1ad 100644 --- a/src/amd/vpelib/src/core/inc/reg_helper.h +++ b/src/amd/vpelib/src/core/inc/reg_helper.h @@ -28,8 +28,8 @@ #pragma once #include -#include "vpe_command.h" #include "config_writer.h" +#include "vpe_command.h" #ifdef __cplusplus extern "C" { diff --git a/src/amd/vpelib/src/core/inc/resource.h b/src/amd/vpelib/src/core/inc/resource.h index c5e74618e32..8c7e49c4435 100644 --- a/src/amd/vpelib/src/core/inc/resource.h +++ b/src/amd/vpelib/src/core/inc/resource.h @@ -41,6 +41,7 @@ struct vpe_cmd_info; struct segment_ctx; #define MAX_PIPE 2 +#define MAX_OUTPUT_PIPE 2 enum vpe_cmd_ops; diff --git a/src/amd/vpelib/src/core/inc/vpe_command.h b/src/amd/vpelib/src/core/inc/vpe_command.h index 06f68c8683e..2f607835b3b 100644 --- a/src/amd/vpelib/src/core/inc/vpe_command.h +++ b/src/amd/vpelib/src/core/inc/vpe_command.h @@ -28,23 +28,25 @@ extern "C" { #endif /**************** - * VPE OP Codes - ****************/ +* VPE OP Codes +****************/ enum VPE_CMD_OPCODE { - VPE_CMD_OPCODE_NOP = 0x0, - VPE_CMD_OPCODE_VPE_DESC = 0x1, - VPE_CMD_OPCODE_PLANE_CFG = 0x2, - VPE_CMD_OPCODE_VPEP_CFG = 0x3, - VPE_CMD_OPCODE_FENCE = 0x5, - VPE_CMD_OPCODE_TRAP = 0x6, - VPE_CMD_OPCODE_REG_WRITE = 0x7, - VPE_CMD_OPCODE_POLL_REGMEM = 0x8, - VPE_CMD_OPCODE_ATOMIC = 0xA, - VPE_CMD_OPCODE_PLANE_FILL = 0xB, + VPE_CMD_OPCODE_NOP = 0x0, + VPE_CMD_OPCODE_VPE_DESC = 0x1, + VPE_CMD_OPCODE_PLANE_CFG = 0x2, + VPE_CMD_OPCODE_VPEP_CFG = 0x3, + VPE_CMD_OPCODE_INDIRECT_BUFFER = 0x4, + VPE_CMD_OPCODE_FENCE = 0x5, + VPE_CMD_OPCODE_TRAP = 0x6, + VPE_CMD_OPCODE_REG_WRITE = 0x7, + VPE_CMD_OPCODE_POLL_REGMEM = 0x8, + VPE_CMD_OPCODE_COND_EXE = 0x9, + VPE_CMD_OPCODE_ATOMIC = 0xA, + VPE_CMD_OPCODE_PLANE_FILL = 0xB, #ifdef VPE_BUILD_1_1 VPE_CMD_OPCODE_COLLABORATE_SYNC = 0xC, #endif - VPE_CMD_OPCODE_TIMESTAMP = 0xD + VPE_CMD_OPCODE_TIMESTAMP = 0xD, }; /** Generic Command Header @@ -62,103 +64,6 @@ enum VPE_CMD_OPCODE { (((subop << VPE_HEADER_SUB_OPCODE__SHIFT) & VPE_HEADER_SUB_OPCODE_MASK) | \ ((op << VPE_HEADER_OPCODE__SHIFT) & VPE_HEADER_OPCODE_MASK)) -/*************************** - * VPE Descriptor - ***************************/ -#define VPE_DESC_CD__SHIFT 16 -#define VPE_DESC_CD_MASK 0x000F0000 - -#define VPE_DESC_ADDR__SHIFT 32 -#define VPE_DESC_HIGH_ADDR_MASK 0xFFFFFFFF00000000 -/* The lowest bits are reuse and tmz as bit 1 and bit 0. - Smibs will substract the address with emb gpuva to - get offset and then reuse bit will be preserved - So as long as the embedded buffer is allocated - at correct alignment (currently low addr is [31:2] - which means we need a 4 byte(2 bit) alignment), - the offset generated will still cover the - reuse bit as part of it. - Ex : Address : 0x200036 GPU Virtual Address : 0x200000 - offset is 0x36 which keeps the reuse bit */ -#define VPE_DESC_LOW_ADDR_MASK 0x00000000FFFFFFFF -#define VPE_DESC_REUSE_TMZ_MASK 0x0000000000000003 - -#define VPE_DESC_NUM_CONFIG_DESCRIPTOR__SHIFT 0 -#define VPE_DESC_NUM_CONFIG_DESCRIPTOR_MASK 0x000000FF - -#define VPE_DESC_REUSE__MASK 0x00000002 - -#define VPE_DESC_CMD_HEADER(cd) \ - (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPE_DESC, 0) | (((cd) << VPE_DESC_CD__SHIFT) & VPE_DESC_CD_MASK)) - -/*************************** - * VPE Plane Config - ***************************/ -enum VPE_PLANE_CFG_SUBOP { - VPE_PLANE_CFG_SUBOP_1_TO_1 = 0x0, - VPE_PLANE_CFG_SUBOP_2_TO_1 = 0x1, - VPE_PLANE_CFG_SUBOP_2_TO_2 = 0x2 -}; - -#define VPE_PLANE_CFG_ONE_PLANE 0 -#define VPE_PLANE_CFG_TWO_PLANES 1 - -#define VPE_PLANE_CFG_NPS0__SHIFT 16 -#define VPE_PLANE_CFG_NPS0_MASK 0x00030000 - -#define VPE_PLANE_CFG_NPD0__SHIFT 18 -#define VPE_PLANE_CFG_NPD0_MASK 0x000C0000 - -#define VPE_PLANE_CFG_NPS1__SHIFT 20 -#define VPE_PLANE_CFG_NPS1_MASK 0x00300000 - -#define VPE_PLANE_CFG_NPD1__SHIFT 22 -#define VPE_PLANE_CFG_NPD1_MASK 0x00C00000 - -#define VPE_PLANE_CFG_TMZ__SHIFT 16 -#define VPE_PLANE_CFG_TMZ_MASK 0x00010000 - -#define VPE_PLANE_CFG_SWIZZLE_MODE__SHIFT 3 -#define VPE_PLANE_CFG_SWIZZLE_MODE_MASK 0x000000F8 - -#define VPE_PLANE_CFG_ROTATION__SHIFT 0 -#define VPE_PLANE_CFG_ROTATION_MASK 0x00000003 - -#define VPE_PLANE_CFG_MIRROR__SHIFT 0 -#define VPE_PLANE_CFG_MIRROR_MASK 0x00000003 - -#define VPE_PLANE_ADDR_LO__SHIFT 0 -#define VPE_PLANE_ADDR_LO_MASK 0xFFFFFF00 - -#define VPE_PLANE_CFG_PITCH__SHIFT 0 -#define VPE_PLANE_CFG_PITCH_MASK 0x00003FFF - -#define VPE_PLANE_CFG_VIEWPORT_Y__SHIFT 16 -#define VPE_PLANE_CFG_VIEWPORT_Y_MASK 0x3FFF0000 -#define VPE_PLANE_CFG_VIEWPORT_X__SHIFT 0 -#define VPE_PLANE_CFG_VIEWPORT_X_MASK 0x00003FFF - -#define VPE_PLANE_CFG_VIEWPORT_HEIGHT__SHIFT 16 -#define VPE_PLANE_CFG_VIEWPORT_HEIGHT_MASK 0x1FFF0000 -#define VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE__SHIFT 13 -#define VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE_MASK 0x0000E000 -#define VPE_PLANE_CFG_VIEWPORT_WIDTH__SHIFT 0 -#define VPE_PLANE_CFG_VIEWPORT_WIDTH_MASK 0x00001FFF - -enum VPE_PLANE_CFG_ELEMENT_SIZE { - VPE_PLANE_CFG_ELEMENT_SIZE_8BPE = 0, - VPE_PLANE_CFG_ELEMENT_SIZE_16BPE = 1, - VPE_PLANE_CFG_ELEMENT_SIZE_32BPE = 2, - VPE_PLANE_CFG_ELEMENT_SIZE_64BPE = 3 -}; - -#define VPE_PLANE_CFG_CMD_HEADER(subop, nps0, npd0, nps1, npd1) \ - (VPE_CMD_HEADER(VPE_CMD_OPCODE_PLANE_CFG, subop) | \ - (((nps0) << VPE_PLANE_CFG_NPS0__SHIFT) & VPE_PLANE_CFG_NPS0_MASK) | \ - (((npd0) << VPE_PLANE_CFG_NPD0__SHIFT) & VPE_PLANE_CFG_NPD0_MASK) | \ - (((nps1) << VPE_PLANE_CFG_NPS1__SHIFT) & VPE_PLANE_CFG_NPS1_MASK) | \ - (((npd0) << VPE_PLANE_CFG_NPD1__SHIFT) & VPE_PLANE_CFG_NPD1_MASK)) - /************************ * VPEP Config ************************/ @@ -174,7 +79,6 @@ enum VPE_VPEP_CFG_SUBOP { #define VPE_DIR_CFG_CMD_HEADER(arr_sz) \ (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPEP_CFG, VPE_VPEP_CFG_SUBOP_DIR_CFG) | \ (((arr_sz) << VPE_DIR_CFG_HEADER_ARRAY_SIZE__SHIFT) & VPE_DIR_CFG_HEADER_ARRAY_SIZE_MASK)) - #define VPE_DIR_CFG_PKT_REGISTER_OFFSET__SHIFT 2 #define VPE_DIR_CFG_PKT_REGISTER_OFFSET_MASK 0x000FFFFC @@ -196,22 +100,11 @@ enum VPE_VPEP_CFG_SUBOP { #define VPE_IND_CFG_PKT_REGISTER_OFFSET__SHIFT 2 #define VPE_IND_CFG_PKT_REGISTER_OFFSET_MASK 0x000FFFFC -#ifdef VPE_BUILD_1_1 -// Collaborate sync Command Header -#define VPE_COLLABORATE_SYNC_HEADER_MASK 0x000000FF -#define VPE_COLLABORATE_SYNC_DATA_MASK(collaborate_data) ((collaborate_data) & 0xFFFFFFFF) -#define VPE_COLLABORATE_SYNC_CMD_HEADER \ - (VPE_CMD_HEADER(VPE_CMD_OPCODE_COLLABORATE_SYNC, 0) & VPE_COLLABORATE_SYNC_HEADER_MASK) -#endif - /************************** - * Poll Reg/Mem Sub-OpCode - **************************/ +* Poll Reg/Mem Sub-OpCode +**************************/ enum VPE_POLL_REGMEM_SUBOP { - VPE_POLL_REGMEM_SUBOP_REGMEM = 0x0, + VPE_POLL_REGMEM_SUBOP_REGMEM = 0x0, VPE_POLL_REGMEM_SUBOP_REGMEM_WRITE = 0x1 }; -#ifdef __cplusplus -} -#endif diff --git a/src/amd/vpelib/src/core/inc/vpe_priv.h b/src/amd/vpelib/src/core/inc/vpe_priv.h index 4b2b5069839..5eaedccc8c1 100644 --- a/src/amd/vpelib/src/core/inc/vpe_priv.h +++ b/src/amd/vpelib/src/core/inc/vpe_priv.h @@ -85,6 +85,11 @@ struct vpe_cmd_input { struct scaler_data scaler_data; }; +struct vpe_cmd_output { + struct vpe_rect dst_viewport; + struct vpe_rect dst_viewport_c; +}; + struct vpe_cmd_info { enum vpe_cmd_ops ops; uint8_t cd; // count down value @@ -94,8 +99,8 @@ struct vpe_cmd_info { struct vpe_cmd_input inputs[MAX_PIPE]; // output - struct vpe_rect dst_viewport; - struct vpe_rect dst_viewport_c; + uint16_t num_outputs; + struct vpe_cmd_output outputs[MAX_OUTPUT_PIPE]; bool tm_enabled; bool insert_start_csync; diff --git a/src/amd/vpelib/src/core/resource.c b/src/amd/vpelib/src/core/resource.c index 93ac8cbc772..9ba8e06961b 100644 --- a/src/amd/vpelib/src/core/resource.c +++ b/src/amd/vpelib/src/core/resource.c @@ -86,19 +86,17 @@ enum vpe_ip_level vpe_resource_parse_ip_version( { enum vpe_ip_level ip_level = VPE_IP_LEVEL_UNKNOWN; switch (VPE_VERSION(major, minor, rev_id)) { -#if VPE_BUILD_1_X -#if VPE_BUILD_1_0 +#ifdef VPE_BUILD_1_0 case VPE_VERSION(6, 1, 0): case VPE_VERSION(6, 1, 3): ip_level = VPE_IP_LEVEL_1_0; break; #endif -#if VPE_BUILD_1_1 +#ifdef VPE_BUILD_1_1 case VPE_VERSION(6, 1, 1): case VPE_VERSION(6, 1, 2): ip_level = VPE_IP_LEVEL_1_1; break; -#endif #endif default: ip_level = VPE_IP_LEVEL_UNKNOWN; diff --git a/src/amd/vpelib/src/core/vpe_desc_writer.c b/src/amd/vpelib/src/core/vpe_desc_writer.c index 53386fe36a1..f8c13a1e354 100644 --- a/src/amd/vpelib/src/core/vpe_desc_writer.c +++ b/src/amd/vpelib/src/core/vpe_desc_writer.c @@ -26,7 +26,7 @@ #include "common.h" #include "reg_helper.h" #include "vpe_desc_writer.h" -#include "vpe_command.h" +#include "vpe10_command.h" void vpe_desc_writer_init(struct vpe_desc_writer *writer, struct vpe_buf *buf, int cd) {