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nvk: Expose cached and coherent as separate types on Tegra

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33959>
This commit is contained in:
Faith Ekstrand 2025-10-14 17:08:11 -04:00
parent 72c1c52b1d
commit cb8cca0145
3 changed files with 40 additions and 11 deletions
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3
src/nouveau/vulkan/nvk_device_memory.c
View file

@ -52,6 +52,9 @@ nvk_memory_type_flags(const VkMemoryType *type,
if (type->propertyFlags & VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT) if (type->propertyFlags & VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)
flags |= NVKMD_MEM_CAN_MAP; flags |= NVKMD_MEM_CAN_MAP;
if (type->propertyFlags & VK_MEMORY_PROPERTY_HOST_COHERENT_BIT)
flags |= NVKMD_MEM_COHERENT;
if (handle_types != 0) if (handle_types != 0)
flags |= NVKMD_MEM_SHARED; flags |= NVKMD_MEM_SHARED;

44
src/nouveau/vulkan/nvk_physical_device.c
View file

@ -1481,20 +1481,42 @@ nvk_create_drm_physical_device(struct vk_instance *_instance,
uint32_t sysmem_heap_idx = pdev->mem_heap_count++; uint32_t sysmem_heap_idx = pdev->mem_heap_count++;
pdev->mem_heaps[sysmem_heap_idx] = (struct nvk_memory_heap) { pdev->mem_heaps[sysmem_heap_idx] = (struct nvk_memory_heap) {
.size = sysmem_size_B, .size = sysmem_size_B,
/* If we don't have any VRAM (iGPU), claim sysmem as DEVICE_LOCAL */ .flags = 0,
.flags = pdev->info.vram_size_B == 0
? VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
: 0,
.available = nvk_get_sysmem_heap_available, .available = nvk_get_sysmem_heap_available,
}; };
pdev->mem_types[pdev->mem_type_count++] = (VkMemoryType) { if (pdev->info.type == NV_DEVICE_TYPE_SOC) {
/* TODO: What's the right thing to do here on Tegra? */ /* On Tegra, we only have sysmem so we claim it's DEVICE_LOCAL. The
.propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | * only difference in memory types is between cached and uncached (but
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT | * coherent) maps.
VK_MEMORY_PROPERTY_HOST_CACHED_BIT, */
.heapIndex = sysmem_heap_idx, assert(pdev->info.vram_size_B == 0);
}; assert(pdev->mem_heap_count == 1);
pdev->mem_heaps[sysmem_heap_idx].flags |= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT;
pdev->mem_types[pdev->mem_type_count++] = (VkMemoryType) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
.heapIndex = sysmem_heap_idx,
};
pdev->mem_types[pdev->mem_type_count++] = (VkMemoryType) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
.heapIndex = sysmem_heap_idx,
};
} else {
/* On discrete GPUs, all sysmem maps are cached+coherent and the GPU
* snoops the CPU caches when it accesses memory across the PCI bus.
*/
pdev->mem_types[pdev->mem_type_count++] = (VkMemoryType) {
.propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
.heapIndex = sysmem_heap_idx,
};
}
assert(pdev->mem_heap_count <= ARRAY_SIZE(pdev->mem_heaps)); assert(pdev->mem_heap_count <= ARRAY_SIZE(pdev->mem_heaps));
assert(pdev->mem_type_count <= ARRAY_SIZE(pdev->mem_types)); assert(pdev->mem_type_count <= ARRAY_SIZE(pdev->mem_types));

4
src/nouveau/winsys/nouveau_device.c
View file

@ -550,6 +550,10 @@ nouveau_ws_device_destroy(struct nouveau_ws_device *device)
uint64_t uint64_t
nouveau_ws_device_vram_used(struct nouveau_ws_device *device) nouveau_ws_device_vram_used(struct nouveau_ws_device *device)
{ {
/* On Tegra, we don't have VRAM */
if (device->info.type == NV_DEVICE_TYPE_SOC)
return 0;
uint64_t used = 0; uint64_t used = 0;
if (nouveau_ws_param(device->fd, NOUVEAU_GETPARAM_VRAM_USED, &used)) if (nouveau_ws_param(device->fd, NOUVEAU_GETPARAM_VRAM_USED, &used))
return 0; return 0;