fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-03 01:18:06 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radv: initialize HiZ for UNDEFINED transitions on transfer queue

Browse source 
This doesn't consider layers/mips because it doesn't seem possible,
but it doesn't hurt correctness either, it just means HiZ is disabled.

This fixes dEQP-VK.api.copy_and_blit.core.use_after_copy.*_tq on GFX12.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40304>
This commit is contained in:
Samuel Pitoiset 2026-03-09 17:18:19 +01:00 • committed by Marge Bot
parent 2b7077b8ba
commit cb5f2a0521
1 changed files with 9 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -14348,11 +14348,9 @@ static void
radv_initialize_hiz(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, const VkImageSubresourceRange *range)
{
struct radv_cmd_state *state = &cmd_buffer->state;
const uint32_t hiz_value = radv_gfx12_get_hiz_initial_value();
struct radv_barrier_data barrier = {0};
if (cmd_buffer->qf == RADV_QUEUE_TRANSFER)
return;
barrier.layout_transitions.init_mask_ram = 1;
radv_describe_layout_transition(cmd_buffer, &barrier);
@ -14361,7 +14359,14 @@ radv_initialize_hiz(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image
state->flush_bits |= radv_src_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT,
VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, 0, image, range);
cmd_buffer->state.flush_bits |= radv_clear_hiz(cmd_buffer, image, range, radv_gfx12_get_hiz_initial_value());
if (cmd_buffer->qf == RADV_QUEUE_TRANSFER) {
const uint64_t hiz_offset = image->planes[0].surface.u.gfx9.zs.hiz.offset;
const uint32_t hiz_size = image->planes[0].surface.u.gfx9.zs.hiz.size;
radv_fill_image(cmd_buffer, image, hiz_offset, hiz_size, hiz_value);
} else {
cmd_buffer->state.flush_bits |= radv_clear_hiz(cmd_buffer, image, range, hiz_value);
}
/* Allow to enable HiZ for this range because all layers are handled in the barrier. */
const bool enable_hiz =