mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-07 07:08:04 +02:00
r300: general cleanup
- remove unused fields - remove unused defines and macros - flatten one structure
This commit is contained in:
parent
b552446b95
commit
cb4bef7ae0
5 changed files with 41 additions and 55 deletions
|
|
@ -37,24 +37,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
#ifndef __R300_CONTEXT_H__
|
||||
#define __R300_CONTEXT_H__
|
||||
|
||||
#include "tnl/t_vertex.h"
|
||||
#include "drm.h"
|
||||
#include "radeon_drm.h"
|
||||
#include "dri_util.h"
|
||||
#include "texmem.h"
|
||||
#include "radeon_common.h"
|
||||
|
||||
#include "main/macros.h"
|
||||
#include "main/mtypes.h"
|
||||
#include "main/colormac.h"
|
||||
|
||||
struct r300_context;
|
||||
typedef struct r300_context r300ContextRec;
|
||||
typedef struct r300_context *r300ContextPtr;
|
||||
|
||||
|
||||
#include "main/mm.h"
|
||||
|
||||
/* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
|
||||
I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
|
||||
with other compilers ... GLUE!
|
||||
|
|
@ -81,9 +75,6 @@ typedef struct r300_context *r300ContextPtr;
|
|||
#define R300_BLIT_WIDTH_BYTES 1024
|
||||
#define R300_MAX_TEXTURE_UNITS 8
|
||||
|
||||
struct r300_texture_state {
|
||||
int tc_count; /* number of incoming texture coordinates from VAP */
|
||||
};
|
||||
|
||||
|
||||
#define R300_VPT_CMD_0 0
|
||||
|
|
@ -303,7 +294,7 @@ struct r300_texture_state {
|
|||
struct r300_hw_state {
|
||||
struct radeon_state_atom vpt; /* viewport (1D98) */
|
||||
struct radeon_state_atom vap_cntl;
|
||||
struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
|
||||
struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
|
||||
struct radeon_state_atom vof; /* VAP output format register 0x2090 */
|
||||
struct radeon_state_atom vte; /* (20B0) */
|
||||
struct radeon_state_atom vap_vf_max_vtx_indx; /* Maximum Vertex Indx Clamp (2134) */
|
||||
|
|
@ -425,12 +416,8 @@ extern int hw_tcl_on;
|
|||
#include "tnl_dd/t_dd_vertex.h"
|
||||
#undef TAG
|
||||
|
||||
//#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
|
||||
#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
|
||||
|
||||
/* Should but doesnt work */
|
||||
//#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
|
||||
|
||||
/* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
|
||||
* Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
|
||||
*/
|
||||
|
|
@ -623,20 +610,6 @@ struct r500_fragment_program {
|
|||
|
||||
#define R300_MAX_AOS_ARRAYS 16
|
||||
|
||||
#define REG_COORDS 0
|
||||
#define REG_COLOR0 1
|
||||
#define REG_TEX0 2
|
||||
|
||||
struct r300_state {
|
||||
struct r300_texture_state texture;
|
||||
int sw_tcl_inputs[VERT_ATTRIB_MAX];
|
||||
struct r300_vertex_shader_state vertex_shader;
|
||||
|
||||
|
||||
DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R300 was configured for.
|
||||
They are the same as tnl->render_inputs for fixed pipeline */
|
||||
|
||||
};
|
||||
|
||||
#define R300_FALLBACK_NONE 0
|
||||
#define R300_FALLBACK_TCL 1
|
||||
|
|
@ -664,6 +637,8 @@ struct r300_swtcl_info {
|
|||
} vert_attrs[VERT_ATTRIB_MAX];
|
||||
|
||||
GLubyte vertex_attr_count;
|
||||
|
||||
int sw_tcl_inputs[VERT_ATTRIB_MAX];
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -675,8 +650,7 @@ struct r300_context {
|
|||
|
||||
struct r300_hw_state hw;
|
||||
|
||||
struct r300_state state;
|
||||
struct gl_vertex_program *curr_vp;
|
||||
struct r300_vertex_shader_state vertex_shader;
|
||||
struct r300_vertex_program *selected_vp;
|
||||
|
||||
/* Vertex buffers
|
||||
|
|
@ -688,6 +662,8 @@ struct r300_context {
|
|||
|
||||
struct r300_swtcl_info swtcl;
|
||||
GLboolean vap_flush_needed;
|
||||
|
||||
DECLARE_RENDERINPUTS(render_inputs_bitset);
|
||||
};
|
||||
|
||||
#define R300_CONTEXT(ctx) ((r300ContextPtr)(ctx->DriverCtx))
|
||||
|
|
@ -703,11 +679,6 @@ extern int r300VertexProgUpdateParams(GLcontext * ctx,
|
|||
struct r300_vertex_program_cont *vp,
|
||||
float *dst);
|
||||
|
||||
#define RADEON_D_CAPTURE 0
|
||||
#define RADEON_D_PLAYBACK 1
|
||||
#define RADEON_D_PLAYBACK_RAW 2
|
||||
#define RADEON_D_T 3
|
||||
|
||||
#define r300PackFloat32 radeonPackFloat32
|
||||
#define r300PackFloat24 radeonPackFloat24
|
||||
|
||||
|
|
|
|||
|
|
@ -127,7 +127,6 @@ GLuint r300VAPInputCntl0(GLcontext * ctx, GLuint InputsRead)
|
|||
|
||||
GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead)
|
||||
{
|
||||
r300ContextPtr rmesa = R300_CONTEXT(ctx);
|
||||
GLuint i, vic_1 = 0;
|
||||
|
||||
if (InputsRead & (1 << VERT_ATTRIB_POS))
|
||||
|
|
@ -139,10 +138,8 @@ GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead)
|
|||
if (InputsRead & (1 << VERT_ATTRIB_COLOR0))
|
||||
vic_1 |= R300_INPUT_CNTL_COLOR;
|
||||
|
||||
rmesa->state.texture.tc_count = 0;
|
||||
for (i = 0; i < ctx->Const.MaxTextureUnits; i++)
|
||||
if (InputsRead & (1 << (VERT_ATTRIB_TEX0 + i))) {
|
||||
rmesa->state.texture.tc_count++;
|
||||
vic_1 |= R300_INPUT_CNTL_TC0 << i;
|
||||
}
|
||||
|
||||
|
|
@ -222,7 +219,7 @@ int r300EmitArrays(GLcontext * ctx)
|
|||
InputsRead = prog->key.InputsRead;
|
||||
OutputsWritten = prog->key.OutputsWritten;
|
||||
} else {
|
||||
inputs = rmesa->state.sw_tcl_inputs;
|
||||
inputs = rmesa->swtcl.sw_tcl_inputs;
|
||||
|
||||
DECLARE_RENDERINPUTS(render_inputs_bitset);
|
||||
RENDERINPUTS_COPY(render_inputs_bitset, tnl->render_inputs_bitset);
|
||||
|
|
@ -275,7 +272,7 @@ int r300EmitArrays(GLcontext * ctx)
|
|||
if (InputsRead & (1 << i))
|
||||
inputs[i] = 6 + (i - VERT_ATTRIB_TEX0);
|
||||
|
||||
RENDERINPUTS_COPY(rmesa->state.render_inputs_bitset, render_inputs_bitset);
|
||||
RENDERINPUTS_COPY(rmesa->render_inputs_bitset, render_inputs_bitset);
|
||||
}
|
||||
|
||||
assert(InputsRead);
|
||||
|
|
@ -330,7 +327,7 @@ int r300EmitArrays(GLcontext * ctx)
|
|||
r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle,
|
||||
nr);
|
||||
}
|
||||
|
||||
|
||||
/* Setup INPUT_CNTL. */
|
||||
R300_STATECHANGE(rmesa, vic);
|
||||
rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead);
|
||||
|
|
|
|||
|
|
@ -1432,7 +1432,7 @@ static void r300SetupRSUnit(GLcontext * ctx)
|
|||
if (hw_tcl_on)
|
||||
OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten;
|
||||
else
|
||||
RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->state.render_inputs_bitset);
|
||||
RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->render_inputs_bitset);
|
||||
|
||||
if (ctx->FragmentProgram._Current)
|
||||
InputsRead = ctx->FragmentProgram._Current->Base.InputsRead;
|
||||
|
|
@ -1583,7 +1583,7 @@ static void r500SetupRSUnit(GLcontext * ctx)
|
|||
if (hw_tcl_on)
|
||||
OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten;
|
||||
else
|
||||
RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->state.render_inputs_bitset);
|
||||
RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->render_inputs_bitset);
|
||||
|
||||
if (ctx->FragmentProgram._Current)
|
||||
InputsRead = ctx->FragmentProgram._Current->Base.InputsRead;
|
||||
|
|
@ -1853,7 +1853,7 @@ static void r300VapCntl(r300ContextPtr rmesa, GLuint input_count,
|
|||
|
||||
static void r300SetupDefaultVertexProgram(r300ContextPtr rmesa)
|
||||
{
|
||||
struct r300_vertex_shader_state *prog = &(rmesa->state.vertex_shader);
|
||||
struct r300_vertex_shader_state *prog = &(rmesa->vertex_shader);
|
||||
GLuint o_reg = 0;
|
||||
GLuint i_reg = 0;
|
||||
int i;
|
||||
|
|
@ -1862,11 +1862,11 @@ static void r300SetupDefaultVertexProgram(r300ContextPtr rmesa)
|
|||
int program_end = 0;
|
||||
|
||||
for (i = VERT_ATTRIB_POS; i < VERT_ATTRIB_MAX; i++) {
|
||||
if (rmesa->state.sw_tcl_inputs[i] != -1) {
|
||||
if (rmesa->swtcl.sw_tcl_inputs[i] != -1) {
|
||||
prog->program.body.i[program_end + 0] = PVS_OP_DST_OPERAND(VE_MULTIPLY, GL_FALSE, GL_FALSE, o_reg++, VSF_FLAG_ALL, PVS_DST_REG_OUT);
|
||||
prog->program.body.i[program_end + 1] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
|
||||
prog->program.body.i[program_end + 2] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
|
||||
prog->program.body.i[program_end + 3] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
|
||||
prog->program.body.i[program_end + 1] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
|
||||
prog->program.body.i[program_end + 2] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
|
||||
prog->program.body.i[program_end + 3] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
|
||||
program_end += 4;
|
||||
i_reg++;
|
||||
}
|
||||
|
|
@ -2522,8 +2522,6 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state)
|
|||
*/
|
||||
void r300InitState(r300ContextPtr r300)
|
||||
{
|
||||
memset(&(r300->state.texture), 0, sizeof(r300->state.texture));
|
||||
|
||||
r300ResetHwState(r300);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -281,7 +281,7 @@ static void r300SetVertexFormat( GLcontext *ctx )
|
|||
|
||||
rmesa->radeon.swtcl.vertex_size /= 4;
|
||||
|
||||
RENDERINPUTS_COPY(rmesa->state.render_inputs_bitset, tnl->render_inputs_bitset);
|
||||
RENDERINPUTS_COPY(rmesa->render_inputs_bitset, tnl->render_inputs_bitset);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -61,21 +61,21 @@ static int radeon_compressed_num_bytes(GLuint mesaFormat)
|
|||
{
|
||||
int bytes = 0;
|
||||
switch(mesaFormat) {
|
||||
|
||||
|
||||
case MESA_FORMAT_RGB_FXT1:
|
||||
case MESA_FORMAT_RGBA_FXT1:
|
||||
case MESA_FORMAT_RGB_DXT1:
|
||||
case MESA_FORMAT_RGBA_DXT1:
|
||||
bytes = 2;
|
||||
break;
|
||||
|
||||
|
||||
case MESA_FORMAT_RGBA_DXT3:
|
||||
case MESA_FORMAT_RGBA_DXT5:
|
||||
bytes = 4;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
return bytes;
|
||||
}
|
||||
|
||||
|
|
@ -97,18 +97,38 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt,
|
|||
lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63;
|
||||
lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx,
|
||||
lvl->width, lvl->height, lvl->depth, mt->compressed);
|
||||
if (lvl->size <= 0) {
|
||||
int *i = 0;
|
||||
*i = 0;
|
||||
}
|
||||
assert(lvl->size > 0);
|
||||
} else if (mt->target == GL_TEXTURE_RECTANGLE_NV) {
|
||||
lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63;
|
||||
lvl->size = lvl->rowstride * lvl->height;
|
||||
if (lvl->size <= 0) {
|
||||
int *i = 0;
|
||||
*i = 0;
|
||||
}
|
||||
assert(lvl->size > 0);
|
||||
} else if (mt->tilebits & RADEON_TXO_MICRO_TILE) {
|
||||
/* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
|
||||
* though the actual offset may be different (if texture is less than
|
||||
* 32 bytes width) to the untiled case */
|
||||
lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31;
|
||||
lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth;
|
||||
if (lvl->size <= 0) {
|
||||
int *i = 0;
|
||||
*i = 0;
|
||||
}
|
||||
assert(lvl->size > 0);
|
||||
} else {
|
||||
lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31;
|
||||
lvl->size = lvl->rowstride * lvl->height * lvl->depth;
|
||||
if (lvl->size <= 0) {
|
||||
int *i = 0;
|
||||
*i = 0;
|
||||
}
|
||||
assert(lvl->size > 0);
|
||||
}
|
||||
assert(lvl->size > 0);
|
||||
|
||||
|
|
@ -230,7 +250,7 @@ static void calculate_first_last_level(struct gl_texture_object *tObj,
|
|||
tObj->Image[face][level];
|
||||
|
||||
assert(baseImage);
|
||||
|
||||
|
||||
/* These must be signed values. MinLod and MaxLod can be negative numbers,
|
||||
* and having firstLevel and lastLevel as signed prevents the need for
|
||||
* extra sign checks.
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue