fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 09:38:07 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

intel: Replace IS_965 checks with context structure usage.

Browse source 
Saves another 600 bytes or so of code.
This commit is contained in:
Eric Anholt 2009-12-16 15:42:55 -08:00
parent 0b87f143c4
commit cb3810dd19
8 changed files with 18 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
src/mesa/drivers/dri/i965/brw_clip_line.c
View file

@ -127,6 +127,7 @@ static void brw_clip_line_alloc_regs( struct brw_clip_compile *c )
static void clip_and_emit_line( struct brw_clip_compile *c )
{
struct brw_compile *p = &c->func;
struct brw_context *brw = p->brw;
struct brw_indirect vtx0 = brw_indirect(0, 0);
struct brw_indirect vtx1 = brw_indirect(1, 0);
struct brw_indirect newvtx0 = brw_indirect(2, 0);
@ -153,7 +154,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
brw_clip_init_clipmask(c);
/* -ve rhw workaround */
if (BRW_IS_965(p->brw)) {
if (brw->has_negative_rhw_bug) {
brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
brw_imm_ud(1<<20));
@ -190,7 +191,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
* Both can be negative on GM965/G965 due to RHW workaround
* if so, this object should be rejected.
*/
if (BRW_IS_965(p->brw)) {
if (brw->has_negative_rhw_bug) {
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE, c->reg.dp0, brw_imm_f(0.0));
is_neg2 = brw_IF(p, BRW_EXECUTE_1);
{
@ -215,7 +216,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
/* If both are positive, do nothing */
/* Only on GM965/G965 */
if (BRW_IS_965(p->brw)) {
if (brw->has_negative_rhw_bug) {
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.dp0, brw_imm_f(0.0));
is_neg2 = brw_IF(p, BRW_EXECUTE_1);
}
@ -230,7 +231,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
}
if (BRW_IS_965(p->brw)) {
if (brw->has_negative_rhw_bug) {
brw_ENDIF(p, is_neg2);
}
}

3
src/mesa/drivers/dri/i965/brw_clip_tri.c
View file

@ -572,6 +572,7 @@ void brw_emit_tri_clip( struct brw_clip_compile *c )
{
struct brw_instruction *neg_rhw;
struct brw_compile *p = &c->func;
struct brw_context *brw = p->brw;
brw_clip_tri_alloc_regs(c, 3 + c->key.nr_userclip + 6);
brw_clip_tri_init_vertices(c);
brw_clip_init_clipmask(c);
@ -579,7 +580,7 @@ void brw_emit_tri_clip( struct brw_clip_compile *c )
/* if -ve rhw workaround bit is set,
do cliptest */
if (BRW_IS_965(p->brw)) {
if (brw->has_negative_rhw_bug) {
brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
brw_imm_ud(1<<20));

4
src/mesa/drivers/dri/i965/brw_context.c
View file

@ -163,11 +163,10 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis,
brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45;
brw->has_surface_tile_offset = GL_TRUE;
brw->has_compr4 = GL_TRUE;
brw->has_aa_line_parameters = GL_TRUE;
} else {
brw->CMD_VF_STATISTICS = CMD_VF_STATISTICS_965;
brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965;
brw->has_surface_tile_offset = GL_FALSE;
brw->has_compr4 = GL_FALSE;
}
/* WM maximum threads is number of EUs times number of threads per EU. */
@ -183,6 +182,7 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis,
brw->urb.size = 256;
brw->vs_max_threads = 16;
brw->wm_max_threads = 8 * 4;
brw->has_negative_rhw_bug = GL_TRUE;
}
if (INTEL_DEBUG & DEBUG_SINGLE_THREAD) {

2
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -440,6 +440,8 @@ struct brw_context
GLboolean emit_state_always;
GLboolean has_surface_tile_offset;
GLboolean has_compr4;
GLboolean has_negative_rhw_bug;
GLboolean has_aa_line_parameters;
;
struct {
struct brw_state_flags dirty;

3
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -832,7 +832,4 @@
#include "intel_chipset.h"
#define BRW_IS_965(brw) (!(brw)->intel.is_g4x && \
!(brw)->intel.is_ironlake)
#endif

4
src/mesa/drivers/dri/i965/brw_misc_state.c
View file

@ -374,8 +374,8 @@ const struct brw_tracked_state brw_polygon_stipple_offset = {
static void upload_aa_line_parameters(struct brw_context *brw)
{
struct brw_aa_line_parameters balp;
if (BRW_IS_965(brw))
if (!brw->has_aa_line_parameters)
return;
/* use legacy aa line coverage computation */

7
src/mesa/drivers/dri/i965/brw_vs_emit.c
View file

@ -1114,7 +1114,8 @@ static void emit_swz( struct brw_vs_compile *c,
static void emit_vertex_write( struct brw_vs_compile *c)
{
struct brw_compile *p = &c->func;
struct intel_context *intel = &p->brw->intel;
struct brw_context *brw = p->brw;
struct intel_context *intel = &brw->intel;
struct brw_reg m0 = brw_message_reg(0);
struct brw_reg pos = c->regs[PROGRAM_OUTPUT][VERT_RESULT_HPOS];
struct brw_reg ndc;
@ -1138,7 +1139,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
* workaround.
*/
if ((c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) ||
c->key.nr_userclip || BRW_IS_965(p->brw))
c->key.nr_userclip || brw->has_negative_rhw_bug)
{
struct brw_reg header1 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD);
GLuint i;
@ -1169,7 +1170,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
* Later, clipping will detect ucp[6] and ensure the primitive is
* clipped against all fixed planes.
*/
if (BRW_IS_965(p->brw)) {
if (brw->has_negative_rhw_bug) {
brw_CMP(p,
vec8(brw_null_reg()),
BRW_CONDITIONAL_L,

2
src/mesa/drivers/dri/intel/intel_extensions.c
View file

@ -196,7 +196,7 @@ intelInitExtensions(GLcontext *ctx)
*/
driInitExtensions(ctx, card_extensions, GL_FALSE);
if (IS_965(intel->intelScreen->deviceID))
if (intel->gen >= 4)
driInitExtensions(ctx, brw_extensions, GL_FALSE);
if (IS_915(intel->intelScreen->deviceID)