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i965: Extend brw_get_rb_for_first_slice() for specified level/layer

Browse source 
v2: Configure stencil directly for final dimensions instead of
    adjusting bit by bit for tiling, mip level and msaa.
v3 (Ken): Used non-static constant for horizontal alignment

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 9d752c098c)
This commit is contained in:
Topi Pohjolainen 2014-04-19 02:02:42 +03:00 • committed by Ian Romanick
parent 43ea5f9347
commit cb37016f89
2 changed files with 29 additions and 7 deletions
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4
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -1475,6 +1475,10 @@ GLboolean brwCreateContext(gl_api api,
/*======================================================================
* brw_misc_state.c
*/
GLuint brw_get_rb_for_slice(struct brw_context *brw,
struct intel_mipmap_tree *mt,
unsigned level, unsigned layer, bool flat);
void brw_meta_updownsample(struct brw_context *brw,
struct intel_mipmap_tree *src,
struct intel_mipmap_tree *dst);

32
src/mesa/drivers/dri/i965/brw_meta_updownsample.c
View file

@ -45,8 +45,10 @@
*
* Clobbers the current renderbuffer binding (ctx->CurrentRenderbuffer).
*/
static GLuint
brw_get_rb_for_first_slice(struct brw_context *brw, struct intel_mipmap_tree *mt)
GLuint
brw_get_rb_for_slice(struct brw_context *brw,
struct intel_mipmap_tree *mt,
unsigned level, unsigned layer, bool flat)
{
struct gl_context *ctx = &brw->ctx;
GLuint rbo;
@ -65,9 +67,25 @@ brw_get_rb_for_first_slice(struct brw_context *brw, struct intel_mipmap_tree *mt
rb->Format = mt->format;
rb->_BaseFormat = _mesa_get_format_base_format(mt->format);
rb->NumSamples = mt->num_samples;
rb->Width = mt->logical_width0;
rb->Height = mt->logical_height0;
/* Program takes care of msaa and mip-level access manually for stencil.
* The surface is also treated as Y-tiled instead of as W-tiled calling for
* twice the width and half the height in dimensions.
*/
if (flat) {
const unsigned halign_stencil = 8;
rb->NumSamples = 0;
rb->Width = ALIGN(mt->total_width, halign_stencil) * 2;
rb->Height = (mt->total_height / mt->physical_depth0) / 2;
irb->mt_level = 0;
} else {
rb->NumSamples = mt->num_samples;
rb->Width = mt->logical_width0;
rb->Height = mt->logical_height0;
irb->mt_level = level;
}
irb->mt_layer = layer;
intel_miptree_reference(&irb->mt, mt);
@ -102,8 +120,8 @@ brw_meta_updownsample(struct brw_context *brw,
_mesa_meta_begin(ctx, MESA_META_ALL);
_mesa_GenFramebuffers(2, fbos);
src_rbo = brw_get_rb_for_first_slice(brw, src_mt);
dst_rbo = brw_get_rb_for_first_slice(brw, dst_mt);
src_rbo = brw_get_rb_for_slice(brw, src_mt, 0, 0, false);
dst_rbo = brw_get_rb_for_slice(brw, dst_mt, 0, 0, false);
src_fbo = fbos[0];
dst_fbo = fbos[1];