diff --git a/src/amd/common/nir/ac_nir_lower_intrinsics_to_args.c b/src/amd/common/nir/ac_nir_lower_intrinsics_to_args.c
index 75b7177358f..065d7b6dac7 100644
--- a/src/amd/common/nir/ac_nir_lower_intrinsics_to_args.c
+++ b/src/amd/common/nir/ac_nir_lower_intrinsics_to_args.c
@@ -339,10 +339,6 @@ lower_intrinsic_to_arg(nir_builder *b, nir_intrinsic_instr *intrin, void *state)
    case nir_intrinsic_load_sample_id:
       replacement = ac_nir_unpack_arg(b, s->args, s->args->ancillary, 8, 4);
       break;
-   case nir_intrinsic_load_sample_pos:
-      replacement = nir_vec2(b, nir_ffract(b, ac_nir_load_arg(b, s->args, s->args->frag_pos[0])),
-                             nir_ffract(b, ac_nir_load_arg(b, s->args, s->args->frag_pos[1])));
-      break;
    case nir_intrinsic_load_frag_shading_rate: {
       /* VRS Rate X = Ancillary[2:3]
        * VRS Rate Y = Ancillary[4:5]
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index a0893ba150f..525cad8e377 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -3770,8 +3770,8 @@ radv_compute_spi_ps_input(enum amd_gfx_level gfx_level, const struct radv_graphi
                   S_0286CC_FRONT_FACE_ENA(info->ps.reads_front_face) |
                   S_0286CC_POS_FIXED_PT_ENA(info->ps.reads_pixel_coord);
 
-   if (info->ps.reads_frag_coord_mask || info->ps.reads_sample_pos_mask) {
-      uint8_t mask = info->ps.reads_frag_coord_mask | info->ps.reads_sample_pos_mask;
+   if (info->ps.reads_frag_coord_mask) {
+      uint8_t mask = info->ps.reads_frag_coord_mask;
 
       for (unsigned i = 0; i < 4; i++) {
          if (mask & (1 << i))
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index 6c98d4dd8da..b90d4ce4b28 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -279,9 +279,6 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr, s
    case nir_intrinsic_load_frag_coord_w_rcp:
       info->ps.reads_frag_coord_mask |= BITFIELD_BIT(3);
       break;
-   case nir_intrinsic_load_sample_pos:
-      info->ps.reads_sample_pos_mask |= nir_def_components_read(&instr->def);
-      break;
    case nir_intrinsic_load_push_constant:
       gather_push_constant_info(nir, instr, info);
       break;
diff --git a/src/amd/vulkan/radv_shader_info.h b/src/amd/vulkan/radv_shader_info.h
index 8d9945a6aea..043e515df97 100644
--- a/src/amd/vulkan/radv_shader_info.h
+++ b/src/amd/vulkan/radv_shader_info.h
@@ -186,7 +186,6 @@ struct radv_shader_info {
       bool early_fragment_test : 1;
       bool post_depth_coverage : 1;
       uint8_t reads_frag_coord_mask;
-      uint8_t reads_sample_pos_mask;
       uint8_t depth_layout;
       bool reads_sample_mask_in : 1;
       bool reads_front_face : 1;