diff --git a/.pick_status.json b/.pick_status.json
index 2b326ca16dc..a70441fd4dd 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -164,7 +164,7 @@
         "description": "iris: Set missing flags on clear color changes",
         "nominated": true,
         "nomination_type": 2,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "64d861b700e4e7dde08027af8f43f7b186489453",
         "notes": null
diff --git a/src/gallium/drivers/iris/iris_clear.c b/src/gallium/drivers/iris/iris_clear.c
index fa0abfb3767..cbac346f915 100644
--- a/src/gallium/drivers/iris/iris_clear.c
+++ b/src/gallium/drivers/iris/iris_clear.c
@@ -303,9 +303,28 @@ fast_clear_color(struct iris_context *ice,
                                  PIPE_CONTROL_RENDER_TARGET_FLUSH);
    }
 
-   /* Update the clear color now that previous rendering is complete. */
-   if (color_changed && res->aux.clear_color_bo)
-      iris_resource_update_indirect_color(batch, res);
+   if (color_changed) {
+      if (devinfo->ver <= 12) {
+         /* A new clear color may require partial resolves later on. */
+         ice->state.dirty |= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES |
+                             IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES;
+         ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS;
+      }
+
+      if (devinfo->ver >= 20) {
+         /* The clear pixel is updated by hardware during fast clears. */
+         assert(batch->screen->isl_dev.ss.clear_color_state_size == 0);
+         assert(batch->screen->isl_dev.ss.clear_value_size == 0);
+      } else if (devinfo->ver >= 11) {
+         /* Update dwords used for rendering and sampling. */
+         assert(batch->screen->isl_dev.ss.clear_color_state_size > 0);
+         iris_resource_update_indirect_color(batch, res);
+      } else {
+         /* We've flagged surface states with inline clear colors as dirty. */
+         assert(batch->screen->isl_dev.ss.clear_value_size > 0);
+         assert(ice->state.stage_dirty & IRIS_ALL_STAGE_DIRTY_BINDINGS);
+      }
+   }
 
    /* If the buffer is already in ISL_AUX_STATE_CLEAR, the clear is redundant
     * and can be skipped.
@@ -388,9 +407,6 @@ fast_clear_color(struct iris_context *ice,
                                box->depth, devinfo->ver < 20 ?
                                ISL_AUX_STATE_CLEAR :
                                ISL_AUX_STATE_COMPRESSED_NO_CLEAR);
-   ice->state.dirty |= IRIS_DIRTY_RENDER_BUFFER;
-   ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS;
-   return;
 }
 
 static void