radv, radeonsi: Move GFX6-7 CB clamp issue to ac_gpu_info

To improve consistency between the two drivers.
This excludes Hawaii from the workaround on RADV.

Also add the same to ac_null_device_create().

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38304>

src/amd/common/ac_gpu_info.c

@@ -961,6 +961,14 @@ ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
     */
    info->has_null_index_buffer_clamping_bug = info->gfx_level == GFX6;
 
+   /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
+    * to the range supported by the type if a channel has less
+    * than 16 bits and the export format is 16_ABGR.
+    * See waCbNoLt16BitIntClamp in PAL.
+    */
+   info->has_cb_lt16bit_int_clamp_bug = info->gfx_level <= GFX7 &&
+                                        info->family != CHIP_HAWAII;
+
    /* Drawing from 0-sized index buffers causes hangs on gfx10. */
    info->has_zero_index_buffer_bug = info->gfx_level == GFX10;
 

src/amd/common/ac_gpu_info.h

@@ -102,6 +102,7 @@ struct radeon_info {
    bool has_ls_vgpr_init_bug;
    bool has_pops_missed_overlap_bug;
    bool has_null_index_buffer_clamping_bug;
+   bool has_cb_lt16bit_int_clamp_bug;
    bool has_zero_index_buffer_bug;
    bool has_image_load_dcc_bug;
    bool has_two_planes_iterate256_bug;

src/amd/common/ac_null_device.c

@@ -84,6 +84,9 @@ ac_null_device_create(struct radeon_info *gpu_info, const char *family)
    gpu_info->has_dedicated_vram = pci_ids[gpu_info->family].has_dedicated_vram;
    gpu_info->has_packed_math_16bit = gpu_info->gfx_level >= GFX9;
 
+   gpu_info->has_cb_lt16bit_int_clamp_bug = gpu_info->gfx_level <= GFX7 &&
+                                            gpu_info->family != CHIP_HAWAII;
+
    gpu_info->has_image_load_dcc_bug = gpu_info->family == CHIP_NAVI23 || gpu_info->family == CHIP_VANGOGH;
 
    gpu_info->has_distributed_tess =

src/amd/vulkan/radv_pipeline_graphics.c

@@ -1889,8 +1889,8 @@ radv_generate_ps_epilog_key(const struct radv_device *device, const struct radv_
                                          state->alpha_to_coverage_via_mrtz);
 
    key.spi_shader_col_format = col_format;
-   key.color_is_int8 = pdev->info.gfx_level < GFX8 ? is_int8 : 0;
+   key.color_is_int8 = pdev->info.has_cb_lt16bit_int_clamp_bug ? is_int8 : 0;
-   key.color_is_int10 = pdev->info.gfx_level < GFX8 ? is_int10 : 0;
+   key.color_is_int10 = pdev->info.has_cb_lt16bit_int_clamp_bug ? is_int10 : 0;
    key.enable_mrt_output_nan_fixup = instance->drirc.debug.enable_mrt_output_nan_fixup ? is_float32 : 0;
    key.colors_written = state->colors_written;
    key.mrt0_is_dual_src = state->mrt0_is_dual_src;

src/gallium/drivers/radeonsi/si_state_shaders.cpp

@@ -2728,11 +2728,8 @@ void si_ps_key_update_framebuffer_blend_dsa_rasterizer(struct si_context *sctx)
        !key->ps.part.epilog.alpha_to_coverage_via_mrtz)
       key->ps.part.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
 
-   /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
+   /* CB doesn't clamp outputs to less than 16 bits. */
-    * to the range supported by the type if a channel has less
+   if (sctx->screen->info.has_cb_lt16bit_int_clamp_bug) {
-    * than 16 bits and the export format is 16_ABGR.
-    */
-   if (sctx->gfx_level <= GFX7 && sctx->family != CHIP_HAWAII) {
       key->ps.part.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
       key->ps.part.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
    }