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panfrost: make sure blends always have 4 components
bi_emit_blend_op has a hardcoded assumption that 4 components were used for blending. This causes validation errors in some situations where fewer components were actually used, because the number of staging registers did not match the number of registers in the actual input. Fix this by extending the source to 4 components. Signed-off-by: Eric R. Smith <eric.smith@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28057>
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1 changed files with 30 additions and 2 deletions
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@ -860,6 +860,33 @@ bi_emit_atest(bi_builder *b, bi_index alpha)
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b->shader->emitted_atest = true;
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}
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static bi_index
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bi_src_color_vec4(bi_builder *b, nir_src *src, nir_alu_type T)
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{
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unsigned num_components = nir_src_num_components(*src);
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bi_index base = bi_src_index(src);
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/* short-circuit the common case */
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if (num_components == 4)
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return base;
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unsigned size = nir_alu_type_get_type_size(T);
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assert(size == 16 || size == 32);
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bi_index src_vals[4];
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unsigned i;
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for (i = 0; i < num_components; i++)
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src_vals[i] = bi_extract(b, base, i);
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for(; i < 3; i++)
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src_vals[i] = (size == 16) ? bi_imm_f16(0.0) : bi_imm_f32(0.0);
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src_vals[3] = (size == 16) ? bi_imm_f16(1.0) : bi_imm_f32(1.0);
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bi_index temp = bi_temp(b->shader);
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bi_make_vec_to(b, temp, src_vals, NULL, 4, size);
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return temp;
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}
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static void
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bi_emit_fragment_out(bi_builder *b, nir_intrinsic_instr *instr)
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{
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@ -922,9 +949,10 @@ bi_emit_fragment_out(bi_builder *b, nir_intrinsic_instr *instr)
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if (emit_blend) {
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unsigned rt = loc ? (loc - FRAG_RESULT_DATA0) : 0;
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bool dual = (writeout & PAN_WRITEOUT_2);
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bi_index color = bi_src_index(&instr->src[0]);
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bi_index color2 = dual ? bi_src_index(&instr->src[4]) : bi_null();
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nir_alu_type T = nir_intrinsic_src_type(instr);
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nir_alu_type T2 = dual ? nir_intrinsic_dest_type(instr) : 0;
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bi_index color = bi_src_color_vec4(b, &instr->src[0], T);
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bi_index color2 = dual ? bi_src_color_vec4(b, &instr->src[4], T2) : bi_null();
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/* Explicit copy since BLEND inputs are precoloured to R0-R3,
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* TODO: maybe schedule around this or implement in RA as a
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