mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-01-19 00:10:27 +01:00
freedreno/ir3: lower arrays to regs
Instead of using load/store_var intrinsics, which can have complex derefs in the case of multi-dimensional arrays, lower these to regs and handle the direct/indirect loads in get_src() and stores in put_dst(). This should let us switch to using nir by default. Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
parent
232fc99544
commit
caa64b24ce
2 changed files with 188 additions and 153 deletions
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@ -400,14 +400,14 @@ struct ir3 {
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struct list_head array_list;
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};
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typedef struct nir_variable nir_variable;
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typedef struct nir_register nir_register;
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struct ir3_array {
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struct list_head node;
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unsigned length;
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unsigned id;
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nir_variable *var;
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nir_register *r;
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/* We track the last write and last access (read or write) to
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* setup dependencies on instructions that read or write the
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@ -98,12 +98,17 @@ struct ir3_compile {
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* duplicate instruction sequences (which our backend does not
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* try to clean up, since that should be done as the NIR stage)
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* we cache the address value generated for a given src value:
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*
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* Note that we have to cache these per alignment, since same
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* src used for an array of vec1 cannot be also used for an
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* array of vec4.
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*/
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struct hash_table *addr_ht;
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struct hash_table *addr_ht[4];
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/* last dst array, for indirect we need to insert a var-store.
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*/
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struct ir3_instruction **last_dst;
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unsigned last_dst_n;
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/* maps nir_block to ir3_block, mostly for the purposes of
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* figuring out the blocks successors
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@ -199,6 +204,11 @@ compile_init(struct ir3_compiler *compiler,
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ctx->s = so->shader->nir;
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}
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/* this needs to be the last pass run, so do this here instead of
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* in ir3_optimize_nir():
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*/
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NIR_PASS_V(ctx->s, nir_lower_locals_to_regs);
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if (fd_mesa_debug & FD_DBG_DISASM) {
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DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
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so->shader->id, so->id, so->type,
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@ -280,30 +290,37 @@ compile_free(struct ir3_compile *ctx)
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}
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static void
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declare_var(struct ir3_compile *ctx, nir_variable *var)
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declare_array(struct ir3_compile *ctx, nir_register *reg)
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{
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unsigned length = glsl_get_length(var->type) * 4; /* always vec4, at least with ttn */
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struct ir3_array *arr = rzalloc(ctx, struct ir3_array);
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arr->id = ++ctx->num_arrays;
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arr->length = length;
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arr->var = var;
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/* NOTE: sometimes we get non array regs, for example for arrays of
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* length 1. See fs-const-array-of-struct-of-array.shader_test. So
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* treat a non-array as if it was an array of length 1.
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*
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* It would be nice if there was a nir pass to convert arrays of
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* length 1 to ssa.
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*/
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arr->length = reg->num_components * MAX2(1, reg->num_array_elems);
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compile_assert(ctx, arr->length > 0);
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arr->r = reg;
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list_addtail(&arr->node, &ctx->ir->array_list);
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}
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static struct ir3_array *
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get_var(struct ir3_compile *ctx, nir_variable *var)
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get_array(struct ir3_compile *ctx, nir_register *reg)
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{
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list_for_each_entry (struct ir3_array, arr, &ctx->ir->array_list, node) {
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if (arr->var == var)
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if (arr->r == reg)
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return arr;
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}
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compile_error(ctx, "bogus var: %s\n", var->name);
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compile_error(ctx, "bogus reg: %s\n", reg->name);
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return NULL;
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}
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/* relative (indirect) if address!=NULL */
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static struct ir3_instruction *
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create_var_load(struct ir3_compile *ctx, struct ir3_array *arr, int n,
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create_array_load(struct ir3_compile *ctx, struct ir3_array *arr, int n,
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struct ir3_instruction *address)
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{
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struct ir3_block *block = ctx->block;
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@ -331,7 +348,7 @@ create_var_load(struct ir3_compile *ctx, struct ir3_array *arr, int n,
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/* relative (indirect) if address!=NULL */
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static struct ir3_instruction *
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create_var_store(struct ir3_compile *ctx, struct ir3_array *arr, int n,
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create_array_store(struct ir3_compile *ctx, struct ir3_array *arr, int n,
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struct ir3_instruction *src, struct ir3_instruction *address)
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{
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struct ir3_block *block = ctx->block;
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@ -349,7 +366,8 @@ create_var_store(struct ir3_compile *ctx, struct ir3_array *arr, int n,
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dst->array.offset = n;
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ir3_reg_create(mov, 0, IR3_REG_SSA)->instr = src;
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ir3_instr_set_address(mov, address);
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if (address)
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ir3_instr_set_address(mov, address);
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arr->last_write = arr->last_access = mov;
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@ -360,51 +378,92 @@ create_var_store(struct ir3_compile *ctx, struct ir3_array *arr, int n,
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* insert in def_ht
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*/
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static struct ir3_instruction **
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__get_dst(struct ir3_compile *ctx, void *key, unsigned n)
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get_dst_ssa(struct ir3_compile *ctx, nir_ssa_def *dst, unsigned n)
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{
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struct ir3_instruction **value =
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ralloc_array(ctx->def_ht, struct ir3_instruction *, n);
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_mesa_hash_table_insert(ctx->def_ht, key, value);
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compile_assert(ctx, !ctx->last_dst);
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ctx->last_dst = value;
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_mesa_hash_table_insert(ctx->def_ht, dst, value);
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return value;
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}
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static struct ir3_instruction **
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get_dst(struct ir3_compile *ctx, nir_dest *dst, unsigned n)
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{
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compile_assert(ctx, dst->is_ssa);
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struct ir3_instruction **value;
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if (dst->is_ssa) {
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return __get_dst(ctx, &dst->ssa, n);
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value = get_dst_ssa(ctx, &dst->ssa, n);
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} else {
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return __get_dst(ctx, dst->reg.reg, n);
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value = ralloc_array(ctx, struct ir3_instruction *, n);
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}
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/* NOTE: in non-ssa case, we don't really need to store last_dst
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* but this helps us catch cases where put_dst() call is forgotten
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*/
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compile_assert(ctx, !ctx->last_dst);
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ctx->last_dst = value;
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ctx->last_dst_n = n;
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return value;
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}
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static struct ir3_instruction * get_addr(struct ir3_compile *ctx, struct ir3_instruction *src, int align);
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static struct ir3_instruction * const *
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get_src(struct ir3_compile *ctx, nir_src *src)
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{
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if (src->is_ssa) {
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struct hash_entry *entry;
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entry = _mesa_hash_table_search(ctx->def_ht, src->ssa);
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compile_assert(ctx, entry);
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return entry->data;
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} else {
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nir_register *reg = src->reg.reg;
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struct ir3_array *arr = get_array(ctx, reg);
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unsigned num_components = arr->r->num_components;
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struct ir3_instruction *addr = NULL;
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struct ir3_instruction **value =
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ralloc_array(ctx, struct ir3_instruction *, num_components);
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if (src->reg.indirect)
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addr = get_addr(ctx, get_src(ctx, src->reg.indirect)[0],
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reg->num_components);
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for (unsigned i = 0; i < num_components; i++) {
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unsigned n = src->reg.base_offset * reg->num_components + i;
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compile_assert(ctx, n < arr->length);
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value[i] = create_array_load(ctx, arr, n, addr);
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}
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return value;
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}
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}
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static void
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put_dst(struct ir3_compile *ctx, nir_dest *dst)
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{
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ctx->last_dst = NULL;
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}
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if (!dst->is_ssa) {
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nir_register *reg = dst->reg.reg;
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struct ir3_array *arr = get_array(ctx, reg);
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unsigned num_components = ctx->last_dst_n;
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struct ir3_instruction *addr = NULL;
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static struct ir3_instruction **
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get_dst_ssa(struct ir3_compile *ctx, nir_ssa_def *dst, unsigned n)
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{
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return __get_dst(ctx, dst, n);
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}
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if (dst->reg.indirect)
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addr = get_addr(ctx, get_src(ctx, dst->reg.indirect)[0],
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reg->num_components);
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static struct ir3_instruction * const *
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get_src(struct ir3_compile *ctx, nir_src *src)
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{
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struct hash_entry *entry;
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compile_assert(ctx, src->is_ssa);
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if (src->is_ssa) {
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entry = _mesa_hash_table_search(ctx->def_ht, src->ssa);
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} else {
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entry = _mesa_hash_table_search(ctx->def_ht, src->reg.reg);
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for (unsigned i = 0; i < num_components; i++) {
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unsigned n = dst->reg.base_offset * reg->num_components + i;
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compile_assert(ctx, n < arr->length);
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if (!ctx->last_dst[i])
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continue;
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create_array_store(ctx, arr, n, ctx->last_dst[i], addr);
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}
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ralloc_free(ctx->last_dst);
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}
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compile_assert(ctx, entry);
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return entry->data;
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ctx->last_dst = NULL;
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ctx->last_dst_n = 0;
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}
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static struct ir3_instruction *
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@ -422,7 +481,7 @@ create_immed(struct ir3_block *block, uint32_t val)
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}
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static struct ir3_instruction *
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create_addr(struct ir3_block *block, struct ir3_instruction *src)
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create_addr(struct ir3_block *block, struct ir3_instruction *src, int align)
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{
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struct ir3_instruction *instr, *immed;
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@ -432,12 +491,41 @@ create_addr(struct ir3_block *block, struct ir3_instruction *src)
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instr = ir3_COV(block, src, TYPE_U32, TYPE_S16);
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instr->regs[0]->flags |= IR3_REG_HALF;
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immed = create_immed(block, 2);
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immed->regs[0]->flags |= IR3_REG_HALF;
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switch(align){
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case 1:
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/* src *= 1: */
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break;
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case 2:
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/* src *= 2 => src <<= 1: */
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immed = create_immed(block, 1);
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immed->regs[0]->flags |= IR3_REG_HALF;
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instr = ir3_SHL_B(block, instr, 0, immed, 0);
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instr->regs[0]->flags |= IR3_REG_HALF;
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instr->regs[1]->flags |= IR3_REG_HALF;
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instr = ir3_SHL_B(block, instr, 0, immed, 0);
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instr->regs[0]->flags |= IR3_REG_HALF;
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instr->regs[1]->flags |= IR3_REG_HALF;
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break;
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case 3:
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/* src *= 3: */
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immed = create_immed(block, 3);
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immed->regs[0]->flags |= IR3_REG_HALF;
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instr = ir3_MULL_U(block, instr, 0, immed, 0);
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instr->regs[0]->flags |= IR3_REG_HALF;
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instr->regs[1]->flags |= IR3_REG_HALF;
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break;
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case 4:
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/* src *= 4 => src <<= 2: */
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immed = create_immed(block, 2);
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immed->regs[0]->flags |= IR3_REG_HALF;
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instr = ir3_SHL_B(block, instr, 0, immed, 0);
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instr->regs[0]->flags |= IR3_REG_HALF;
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instr->regs[1]->flags |= IR3_REG_HALF;
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break;
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default:
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unreachable("bad align");
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return NULL;
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}
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instr = ir3_MOV(block, instr, TYPE_S16);
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instr->regs[0]->num = regid(REG_A0, 0);
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@ -451,22 +539,25 @@ create_addr(struct ir3_block *block, struct ir3_instruction *src)
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* sequences for each use of a given NIR level src as address
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*/
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static struct ir3_instruction *
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get_addr(struct ir3_compile *ctx, struct ir3_instruction *src)
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get_addr(struct ir3_compile *ctx, struct ir3_instruction *src, int align)
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{
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struct ir3_instruction *addr;
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unsigned idx = align - 1;
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if (!ctx->addr_ht) {
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ctx->addr_ht = _mesa_hash_table_create(ctx,
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compile_assert(ctx, idx < ARRAY_SIZE(ctx->addr_ht));
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if (!ctx->addr_ht[idx]) {
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ctx->addr_ht[idx] = _mesa_hash_table_create(ctx,
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_mesa_hash_pointer, _mesa_key_pointer_equal);
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} else {
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struct hash_entry *entry;
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entry = _mesa_hash_table_search(ctx->addr_ht, src);
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entry = _mesa_hash_table_search(ctx->addr_ht[idx], src);
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if (entry)
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return entry->data;
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}
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addr = create_addr(ctx->block, src);
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_mesa_hash_table_insert(ctx->addr_ht, src, addr);
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addr = create_addr(ctx->block, src, align);
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_mesa_hash_table_insert(ctx->addr_ht[idx], src, addr);
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return addr;
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}
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@ -725,8 +816,17 @@ emit_alu(struct ir3_compile *ctx, nir_alu_instr *alu)
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const nir_op_info *info = &nir_op_infos[alu->op];
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struct ir3_instruction **dst, *src[info->num_inputs];
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struct ir3_block *b = ctx->block;
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unsigned dst_sz, wrmask;
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dst = get_dst(ctx, &alu->dest.dest, MAX2(info->output_size, 1));
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if (alu->dest.dest.is_ssa) {
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dst_sz = alu->dest.dest.ssa.num_components;
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wrmask = (1 << dst_sz) - 1;
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} else {
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dst_sz = alu->dest.dest.reg.reg->num_components;
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wrmask = alu->dest.write_mask;
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}
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dst = get_dst(ctx, &alu->dest.dest, dst_sz);
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/* Vectors are special in that they have non-scalarized writemasks,
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* and just take the first swizzle channel for each argument in
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@ -752,6 +852,28 @@ emit_alu(struct ir3_compile *ctx, nir_alu_instr *alu)
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return;
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}
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/* We also get mov's with more than one component for mov's so
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* handle those specially:
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*/
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if ((alu->op == nir_op_imov) || (alu->op == nir_op_fmov)) {
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type_t type = (alu->op == nir_op_imov) ? TYPE_U32 : TYPE_F32;
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nir_alu_src *asrc = &alu->src[0];
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struct ir3_instruction *const *src0 = get_src(ctx, &asrc->src);
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for (unsigned i = 0; i < dst_sz; i++) {
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if (wrmask & (1 << i)) {
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dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], type);
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} else {
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dst[i] = NULL;
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}
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}
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put_dst(ctx, &alu->dest.dest);
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return;
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}
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compile_assert(ctx, alu->dest.dest.is_ssa);
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/* General case: We can just grab the one used channel per src. */
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for (int i = 0; i < info->num_inputs; i++) {
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unsigned chan = ffs(alu->dest.write_mask) - 1;
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@ -778,12 +900,6 @@ emit_alu(struct ir3_compile *ctx, nir_alu_instr *alu)
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case nir_op_u2f32:
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dst[0] = ir3_COV(b, src[0], TYPE_U32, TYPE_F32);
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break;
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case nir_op_imov:
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dst[0] = ir3_MOV(b, src[0], TYPE_S32);
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break;
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case nir_op_fmov:
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dst[0] = ir3_MOV(b, src[0], TYPE_F32);
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break;
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case nir_op_f2b:
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dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
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dst[0]->cat2.condition = IR3_COND_NE;
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@ -1054,8 +1170,8 @@ emit_intrinsic_load_ubo(struct ir3_compile *ctx, nir_intrinsic_instr *intr,
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base_lo = create_uniform(ctx, ubo + (src0->regs[1]->iim_val * ptrsz));
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base_hi = create_uniform(ctx, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
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} else {
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base_lo = create_uniform_indirect(ctx, ubo, get_addr(ctx, src0));
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base_hi = create_uniform_indirect(ctx, ubo + 1, get_addr(ctx, src0));
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base_lo = create_uniform_indirect(ctx, ubo, get_addr(ctx, src0, 4));
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base_hi = create_uniform_indirect(ctx, ubo + 1, get_addr(ctx, src0, 4));
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}
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/* note: on 32bit gpu's base_hi is ignored and DCE'd */
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@ -1105,83 +1221,6 @@ emit_intrinsic_load_ubo(struct ir3_compile *ctx, nir_intrinsic_instr *intr,
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}
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}
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/* handles array reads: */
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static void
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emit_intrinsic_load_var(struct ir3_compile *ctx, nir_intrinsic_instr *intr,
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struct ir3_instruction **dst)
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{
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nir_deref_var *dvar = intr->variables[0];
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nir_deref_array *darr = nir_deref_as_array(dvar->deref.child);
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struct ir3_array *arr = get_var(ctx, dvar->var);
|
||||
|
||||
compile_assert(ctx, dvar->deref.child &&
|
||||
(dvar->deref.child->deref_type == nir_deref_type_array));
|
||||
|
||||
switch (darr->deref_array_type) {
|
||||
case nir_deref_array_type_direct:
|
||||
/* direct access does not require anything special: */
|
||||
for (int i = 0; i < intr->num_components; i++) {
|
||||
unsigned n = darr->base_offset * 4 + i;
|
||||
compile_assert(ctx, n < arr->length);
|
||||
dst[i] = create_var_load(ctx, arr, n, NULL);
|
||||
}
|
||||
break;
|
||||
case nir_deref_array_type_indirect: {
|
||||
/* for indirect, we need to collect all the array elements: */
|
||||
struct ir3_instruction *addr =
|
||||
get_addr(ctx, get_src(ctx, &darr->indirect)[0]);
|
||||
for (int i = 0; i < intr->num_components; i++) {
|
||||
unsigned n = darr->base_offset * 4 + i;
|
||||
compile_assert(ctx, n < arr->length);
|
||||
dst[i] = create_var_load(ctx, arr, n, addr);
|
||||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
compile_error(ctx, "Unhandled load deref type: %u\n",
|
||||
darr->deref_array_type);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* handles array writes: */
|
||||
static void
|
||||
emit_intrinsic_store_var(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
|
||||
{
|
||||
nir_deref_var *dvar = intr->variables[0];
|
||||
nir_deref_array *darr = nir_deref_as_array(dvar->deref.child);
|
||||
struct ir3_array *arr = get_var(ctx, dvar->var);
|
||||
struct ir3_instruction *addr;
|
||||
struct ir3_instruction * const *src;
|
||||
unsigned wrmask = nir_intrinsic_write_mask(intr);
|
||||
|
||||
compile_assert(ctx, dvar->deref.child &&
|
||||
(dvar->deref.child->deref_type == nir_deref_type_array));
|
||||
|
||||
src = get_src(ctx, &intr->src[0]);
|
||||
|
||||
switch (darr->deref_array_type) {
|
||||
case nir_deref_array_type_direct:
|
||||
addr = NULL;
|
||||
break;
|
||||
case nir_deref_array_type_indirect:
|
||||
addr = get_addr(ctx, get_src(ctx, &darr->indirect)[0]);
|
||||
break;
|
||||
default:
|
||||
compile_error(ctx, "Unhandled store deref type: %u\n",
|
||||
darr->deref_array_type);
|
||||
return;
|
||||
}
|
||||
|
||||
for (int i = 0; i < intr->num_components; i++) {
|
||||
if (!(wrmask & (1 << i)))
|
||||
continue;
|
||||
unsigned n = darr->base_offset * 4 + i;
|
||||
compile_assert(ctx, n < arr->length);
|
||||
create_var_store(ctx, arr, n, src[i], addr);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
mark_ssbo_read(struct ir3_compile *ctx, struct ir3_instruction *instr)
|
||||
{
|
||||
|
|
@ -1399,7 +1438,7 @@ emit_intrinsic(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
|
|||
for (int i = 0; i < intr->num_components; i++) {
|
||||
int n = idx * 4 + i;
|
||||
dst[i] = create_uniform_indirect(ctx, n,
|
||||
get_addr(ctx, src[0]));
|
||||
get_addr(ctx, src[0], 4));
|
||||
}
|
||||
/* NOTE: if relative addressing is used, we set
|
||||
* constlen in the compiler (to worst-case value)
|
||||
|
|
@ -1425,7 +1464,7 @@ emit_intrinsic(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
|
|||
src = get_src(ctx, &intr->src[0]);
|
||||
struct ir3_instruction *collect =
|
||||
create_collect(b, ctx->ir->inputs, ctx->ir->ninputs);
|
||||
struct ir3_instruction *addr = get_addr(ctx, src[0]);
|
||||
struct ir3_instruction *addr = get_addr(ctx, src[0], 4);
|
||||
for (int i = 0; i < intr->num_components; i++) {
|
||||
unsigned n = idx * 4 + i;
|
||||
dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
|
||||
|
|
@ -1433,12 +1472,6 @@ emit_intrinsic(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
|
|||
}
|
||||
}
|
||||
break;
|
||||
case nir_intrinsic_load_var:
|
||||
emit_intrinsic_load_var(ctx, intr, dst);
|
||||
break;
|
||||
case nir_intrinsic_store_var:
|
||||
emit_intrinsic_store_var(ctx, intr);
|
||||
break;
|
||||
case nir_intrinsic_load_ssbo:
|
||||
emit_intrinsic_load_ssbo(ctx, intr, dst);
|
||||
break;
|
||||
|
|
@ -1933,6 +1966,8 @@ emit_tex_txs(struct ir3_compile *ctx, nir_tex_instr *tex)
|
|||
dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
|
||||
}
|
||||
}
|
||||
|
||||
put_dst(ctx, &tex->dest);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -2088,8 +2123,10 @@ emit_block(struct ir3_compile *ctx, nir_block *nblock)
|
|||
list_addtail(&block->node, &ctx->ir->block_list);
|
||||
|
||||
/* re-emit addr register in each block if needed: */
|
||||
_mesa_hash_table_destroy(ctx->addr_ht, NULL);
|
||||
ctx->addr_ht = NULL;
|
||||
for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
|
||||
_mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
|
||||
ctx->addr_ht[i] = NULL;
|
||||
}
|
||||
|
||||
nir_foreach_instr(instr, nblock) {
|
||||
emit_instr(ctx, instr);
|
||||
|
|
@ -2508,17 +2545,15 @@ emit_instructions(struct ir3_compile *ctx)
|
|||
setup_output(ctx, var);
|
||||
}
|
||||
|
||||
/* Setup global variables (which should only be arrays): */
|
||||
nir_foreach_variable(var, &ctx->s->globals) {
|
||||
declare_var(ctx, var);
|
||||
/* Setup registers (which should only be arrays): */
|
||||
nir_foreach_register(reg, &ctx->s->registers) {
|
||||
declare_array(ctx, reg);
|
||||
}
|
||||
|
||||
/* Setup local variables (which should only be arrays): */
|
||||
/* NOTE: need to do something more clever when we support >1 fxn */
|
||||
nir_foreach_variable(var, &fxn->locals) {
|
||||
declare_var(ctx, var);
|
||||
nir_foreach_register(reg, &fxn->registers) {
|
||||
declare_array(ctx, reg);
|
||||
}
|
||||
|
||||
/* And emit the body: */
|
||||
ctx->impl = fxn;
|
||||
emit_function(ctx, fxn);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue