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intel/brw/xe3: Define XE3_MAX_GRF.

Browse source 
Gfx30 supports up to 256 (512b) GRFs which requires a max GRF define
of 512 in REG_SIZE units.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32664>
This commit is contained in:
Francisco Jerez 2024-09-18 14:25:30 -07:00 • committed by Marge Bot
parent 67cb23a4b1
commit ca1636d457
4 changed files with 11 additions and 10 deletions
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14
src/intel/compiler/brw_eu_emit.c
View file

@ -41,7 +41,7 @@ brw_set_dest(struct brw_codegen *p, brw_eu_inst *inst, struct brw_reg dest)
const struct intel_device_info *devinfo = p->devinfo;
if (dest.file == FIXED_GRF)
assert(dest.nr < XE2_MAX_GRF);
assert(dest.nr < XE3_MAX_GRF);
/* The hardware has a restriction where a destination of size Byte with
* a stride of 1 is only allowed for a packed byte MOV. For any other
@ -135,7 +135,7 @@ brw_set_src0(struct brw_codegen *p, brw_eu_inst *inst, struct brw_reg reg)
const struct intel_device_info *devinfo = p->devinfo;
if (reg.file == FIXED_GRF)
assert(reg.nr < XE2_MAX_GRF);
assert(reg.nr < XE3_MAX_GRF);
if (brw_eu_inst_opcode(p->isa, inst) == BRW_OPCODE_SEND ||
brw_eu_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDC ||
@ -260,7 +260,7 @@ brw_set_src1(struct brw_codegen *p, brw_eu_inst *inst, struct brw_reg reg)
const struct intel_device_info *devinfo = p->devinfo;
if (reg.file == FIXED_GRF)
assert(reg.nr < XE2_MAX_GRF);
assert(reg.nr < XE3_MAX_GRF);
if (brw_eu_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDS ||
brw_eu_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDSC ||
@ -555,7 +555,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
const struct intel_device_info *devinfo = p->devinfo;
brw_eu_inst *inst = next_insn(p, opcode);
assert(dest.nr < XE2_MAX_GRF);
assert(dest.nr < XE3_MAX_GRF);
if (devinfo->ver <= 9) {
assert(src0.file != IMM && src2.file != IMM);
@ -579,9 +579,9 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
assert(opcode != BRW_OPCODE_BFI2 ||
(src0.file != IMM && src2.file != IMM));
assert(src0.file == IMM || src0.nr < XE2_MAX_GRF);
assert(src1.file != IMM && src1.nr < XE2_MAX_GRF);
assert(src2.file == IMM || src2.nr < XE2_MAX_GRF);
assert(src0.file == IMM || src0.nr < XE3_MAX_GRF);
assert(src1.file != IMM && src1.nr < XE3_MAX_GRF);
assert(src2.file == IMM || src2.nr < XE3_MAX_GRF);
assert(dest.address_mode == BRW_ADDRESS_DIRECT);
assert(src0.address_mode == BRW_ADDRESS_DIRECT);
assert(src1.address_mode == BRW_ADDRESS_DIRECT);

2
src/intel/compiler/brw_ir_performance.cpp
View file

@ -71,7 +71,7 @@ namespace {
/* Register part of the GRF. */
EU_DEPENDENCY_ID_GRF0 = 0,
/* Address register part of the ARF. */
EU_DEPENDENCY_ID_ADDR0 = EU_DEPENDENCY_ID_GRF0 + XE2_MAX_GRF,
EU_DEPENDENCY_ID_ADDR0 = EU_DEPENDENCY_ID_GRF0 + XE3_MAX_GRF,
/* Accumulator register part of the ARF. */
EU_DEPENDENCY_ID_ACCUM0 = EU_DEPENDENCY_ID_ADDR0 + 1,
/* Flag register part of the ARF. */

2
src/intel/compiler/brw_lower_scoreboard.cpp
View file

@ -756,7 +756,7 @@ namespace {
}
private:
dependency grf_deps[XE2_MAX_GRF];
dependency grf_deps[XE3_MAX_GRF];
dependency addr_dep;
dependency accum_dep;

3
src/intel/compiler/brw_reg.h
View file

@ -59,6 +59,7 @@ struct intel_device_info;
/** Size of general purpose register space in REG_SIZE units */
#define BRW_MAX_GRF 128
#define XE2_MAX_GRF 256
#define XE3_MAX_GRF 512
/**
* BRW hardware swizzles.
@ -416,7 +417,7 @@ brw_make_reg(enum brw_reg_file file,
{
struct brw_reg reg;
if (file == FIXED_GRF)
assert(nr < XE2_MAX_GRF);
assert(nr < XE3_MAX_GRF);
else if (file == ARF)
assert(nr <= BRW_ARF_TIMESTAMP);