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radeonsi/gfx9: handle GFX9 in a few places

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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2016-10-15 14:17:56 +02:00
parent 92112ec296
commit c9b004af58
4 changed files with 5 additions and 2 deletions
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4
src/gallium/drivers/radeonsi/cik_sdma.c
View file

@ -429,9 +429,9 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
dsty % 8 == 0 &&
srcx % 8 == 0 &&
srcy % 8 == 0 &&
/* this can either be equal, or display->rotated (VI only) */
/* this can either be equal, or display->rotated (VI+ only) */
(src_micro_mode == dst_micro_mode ||
(sctx->b.chip_class == VI &&
(sctx->b.chip_class >= VI &&
src_micro_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING &&
dst_micro_mode == V_009910_ADDR_SURF_ROTATED_MICRO_TILING))) {
assert(src_pitch % 8 == 0);

1
src/gallium/drivers/radeonsi/si_perfcounter.c
View file

@ -672,6 +672,7 @@ void si_init_perfcounters(struct si_screen *screen)
num_blocks = ARRAY_SIZE(groups_VI);
break;
case SI:
case GFX9:
default:
return; /* not implemented */
}

1
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -731,6 +731,7 @@ static bool si_init_gs_info(struct si_screen *sscreen)
case CHIP_POLARIS10:
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGA10:
sscreen->gs_table_depth = 32;
return true;
default:

1
src/gallium/drivers/radeonsi/si_state_shaders.c
View file

@ -2391,6 +2391,7 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
max_offchip_buffers = MIN2(max_offchip_buffers, 126);
break;
case CIK:
case GFX9:
max_offchip_buffers = MIN2(max_offchip_buffers, 508);
break;
case VI: