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radeonsi/gfx11: buffer descriptor changes

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Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
This commit is contained in:
Marek Olšák 2021-12-18 09:07:48 -05:00 • committed by Marge Bot
parent c87da5c80d
commit c99b71039a
5 changed files with 35 additions and 13 deletions
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10
src/gallium/drivers/radeonsi/si_compute.c
View file

@ -594,15 +594,19 @@ static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
uint32_t scratch_dword0 = scratch_va & 0xffffffff;
uint32_t scratch_dword1 =
S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | S_008F04_SWIZZLE_ENABLE_GFX6(1);
uint32_t scratch_dword1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
if (sctx->chip_class >= GFX11)
scratch_dword1 |= S_008F04_SWIZZLE_ENABLE_GFX11(1);
else
scratch_dword1 |= S_008F04_SWIZZLE_ENABLE_GFX6(1);
/* Disable address clamping */
uint32_t scratch_dword2 = 0xffffffff;
uint32_t scratch_dword3 = S_008F0C_INDEX_STRIDE(3) | S_008F0C_ADD_TID_ENABLE(1);
if (sctx->chip_class >= GFX9) {
assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
assert(max_private_element_size == 1); /* only 4 bytes on GFX9 */
} else {
scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);

25
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -1080,7 +1080,10 @@ static void si_init_buffer_resources(struct si_context *sctx,
desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
if (sctx->chip_class >= GFX10) {
if (sctx->chip_class >= GFX11) {
desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) |
S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW);
} else if (sctx->chip_class >= GFX10) {
desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) |
S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1);
} else {
@ -1532,19 +1535,27 @@ void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource
/* Set the descriptor. */
uint32_t *desc = descs->list + slot * 4;
desc[0] = va;
desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride) |
S_008F04_SWIZZLE_ENABLE_GFX6(swizzle);
desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
desc[2] = num_records;
desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
S_008F0C_INDEX_STRIDE(index_stride) | S_008F0C_ADD_TID_ENABLE(add_tid);
if (sctx->chip_class >= GFX9)
assert(!swizzle || element_size == 1); /* always 4 bytes on GFX9 */
else
if (sctx->chip_class >= GFX11) {
assert(!swizzle || element_size == 1 || element_size == 3); /* 4 or 16 bytes */
desc[1] |= S_008F04_SWIZZLE_ENABLE_GFX11(swizzle ? element_size : 0);
} else if (sctx->chip_class >= GFX9) {
assert(!swizzle || element_size == 1); /* only 4 bytes on GFX9 */
desc[1] |= S_008F04_SWIZZLE_ENABLE_GFX6(swizzle);
} else {
desc[1] |= S_008F04_SWIZZLE_ENABLE_GFX6(swizzle);
desc[3] |= S_008F0C_ELEMENT_SIZE(element_size);
}
if (sctx->chip_class >= GFX10) {
if (sctx->chip_class >= GFX11) {
desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) |
S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED);
} else if (sctx->chip_class >= GFX10) {
desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) |
S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1);
} else {

5
src/gallium/drivers/radeonsi/si_shader_llvm_resources.c
View file

@ -72,7 +72,10 @@ static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *c
uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
if (ctx->screen->info.chip_class >= GFX10)
if (ctx->screen->info.chip_class >= GFX11)
rsrc3 |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) |
S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW);
else if (ctx->screen->info.chip_class >= GFX10)
rsrc3 |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) |
S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1);
else

5
src/gallium/drivers/radeonsi/si_shader_llvm_tess.c
View file

@ -357,7 +357,10 @@ static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx, enum
uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
if (ctx->screen->info.chip_class >= GFX10)
if (ctx->screen->info.chip_class >= GFX11)
rsrc3 |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) |
S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW);
else if (ctx->screen->info.chip_class >= GFX10)
rsrc3 |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) |
S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1);
else

3
src/gallium/drivers/radeonsi/si_state.c
View file

@ -4937,7 +4937,8 @@ static void *si_create_vertex_elements(struct pipe_context *ctx, unsigned count,
if (sscreen->info.chip_class >= GFX10) {
const struct gfx10_format *fmt = &ac_get_gfx10_format_table(&sscreen->info)[elements[i].src_format];
assert(fmt->img_format != 0 && fmt->img_format < 128);
v->rsrc_word3[i] |= S_008F0C_FORMAT(fmt->img_format) | S_008F0C_RESOURCE_LEVEL(1);
v->rsrc_word3[i] |= S_008F0C_FORMAT(fmt->img_format) |
S_008F0C_RESOURCE_LEVEL(sscreen->info.chip_class < GFX11);
} else {
unsigned data_format, num_format;
data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);