From c97bd17d4d8b78f0d3b3236858f648addc578a9d Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 4 Dec 2025 13:08:58 +0100 Subject: [PATCH] radv: switch to AC_TRACKED_xxx Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 242 +++++++++++++++---------------- src/amd/vulkan/radv_cmd_buffer.h | 110 +------------- src/amd/vulkan/radv_cs.c | 2 +- 3 files changed, 122 insertions(+), 232 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 80a681609d7..b90a94ec337 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2603,7 +2603,7 @@ radv_emit_binning_state(struct radv_cmd_buffer *cmd_buffer) const uint32_t pa_sc_binner_cntl_0 = radv_get_binning_state(cmd_buffer); radeon_begin(cs); - radeon_opt_set_context_reg(R_028C44_PA_SC_BINNER_CNTL_0, RADV_TRACKED_PA_SC_BINNER_CNTL_0, pa_sc_binner_cntl_0); + radeon_opt_set_context_reg(R_028C44_PA_SC_BINNER_CNTL_0, AC_TRACKED_PA_SC_BINNER_CNTL_0, pa_sc_binner_cntl_0); radeon_end(); } } @@ -2845,7 +2845,7 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer) * performance. */ radeon_begin(cs); - radeon_opt_set_context_reg3(R_028754_SX_PS_DOWNCONVERT, RADV_TRACKED_SX_PS_DOWNCONVERT, sx_ps_downconvert, + radeon_opt_set_context_reg3(R_028754_SX_PS_DOWNCONVERT, AC_TRACKED_SX_PS_DOWNCONVERT, sx_ps_downconvert, sx_blend_opt_epsilon, sx_blend_opt_control); radeon_end(); } @@ -2938,8 +2938,8 @@ radv_emit_vgt_gs_mode(struct radv_cmd_buffer *cmd_buffer) } radeon_begin(cs); - radeon_opt_set_context_reg(R_028A84_VGT_PRIMITIVEID_EN, RADV_TRACKED_VGT_PRIMITIVEID_EN, vgt_primitiveid_en); - radeon_opt_set_context_reg(R_028A40_VGT_GS_MODE, RADV_TRACKED_VGT_GS_MODE, vgt_gs_mode); + radeon_opt_set_context_reg(R_028A84_VGT_PRIMITIVEID_EN, AC_TRACKED_VGT_PRIMITIVEID_EN, vgt_primitiveid_en); + radeon_opt_set_context_reg(R_028A40_VGT_GS_MODE, AC_TRACKED_VGT_GS_MODE, vgt_gs_mode); radeon_end(); } @@ -2958,15 +2958,13 @@ radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *sh radeon_emit(shader->config.rsrc1); radeon_emit(shader->config.rsrc2); - radeon_opt_set_context_reg(R_0286C4_SPI_VS_OUT_CONFIG, RADV_TRACKED_SPI_VS_OUT_CONFIG, - shader->regs.spi_vs_out_config); - radeon_opt_set_context_reg(R_02870C_SPI_SHADER_POS_FORMAT, RADV_TRACKED_SPI_SHADER_POS_FORMAT, + radeon_opt_set_context_reg(R_0286C4_SPI_VS_OUT_CONFIG, AC_TRACKED_SPI_VS_OUT_CONFIG, shader->regs.spi_vs_out_config); + radeon_opt_set_context_reg(R_02870C_SPI_SHADER_POS_FORMAT, AC_TRACKED_SPI_SHADER_POS_FORMAT, shader->regs.spi_shader_pos_format); - radeon_opt_set_context_reg(R_02881C_PA_CL_VS_OUT_CNTL, RADV_TRACKED_PA_CL_VS_OUT_CNTL, - shader->regs.pa_cl_vs_out_cntl); + radeon_opt_set_context_reg(R_02881C_PA_CL_VS_OUT_CNTL, AC_TRACKED_PA_CL_VS_OUT_CNTL, shader->regs.pa_cl_vs_out_cntl); if (pdev->info.gfx_level <= GFX8) - radeon_opt_set_context_reg(R_028AB4_VGT_REUSE_OFF, RADV_TRACKED_VGT_REUSE_OFF, shader->regs.vs.vgt_reuse_off); + radeon_opt_set_context_reg(R_028AB4_VGT_REUSE_OFF, AC_TRACKED_VGT_REUSE_OFF, shader->regs.vs.vgt_reuse_off); if (pdev->info.gfx_level >= GFX7) { radeon_set_sh_reg_idx(&pdev->info, R_00B118_SPI_SHADER_PGM_RSRC3_VS, 3, shader->regs.vs.spi_shader_pgm_rsrc3_vs); @@ -2976,7 +2974,7 @@ radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *sh radeon_set_uconfig_reg(R_030980_GE_PC_ALLOC, shader->regs.ge_pc_alloc); if (shader->info.stage == MESA_SHADER_TESS_EVAL) { - radeon_opt_set_context_reg(R_028A44_VGT_GS_ONCHIP_CNTL, RADV_TRACKED_VGT_GS_ONCHIP_CNTL, + radeon_opt_set_context_reg(R_028A44_VGT_GS_ONCHIP_CNTL, AC_TRACKED_VGT_GS_ONCHIP_CNTL, shader->regs.vgt_gs_onchip_cntl); } } @@ -3072,52 +3070,52 @@ radv_emit_hw_ngg(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *e if (pdev->info.gfx_level >= GFX12) { radeon_begin(cs); gfx12_begin_context_regs(); - gfx12_opt_set_context_reg(R_028818_PA_CL_VS_OUT_CNTL, RADV_TRACKED_PA_CL_VS_OUT_CNTL, + gfx12_opt_set_context_reg(R_028818_PA_CL_VS_OUT_CNTL, AC_TRACKED_PA_CL_VS_OUT_CNTL, shader->regs.pa_cl_vs_out_cntl); - gfx12_opt_set_context_reg(R_028B3C_VGT_GS_INSTANCE_CNT, RADV_TRACKED_VGT_GS_INSTANCE_CNT, + gfx12_opt_set_context_reg(R_028B3C_VGT_GS_INSTANCE_CNT, AC_TRACKED_VGT_GS_INSTANCE_CNT, shader->regs.vgt_gs_instance_cnt); - gfx12_opt_set_context_reg2(R_028648_SPI_SHADER_IDX_FORMAT, RADV_TRACKED_SPI_SHADER_IDX_FORMAT, + gfx12_opt_set_context_reg2(R_028648_SPI_SHADER_IDX_FORMAT, AC_TRACKED_SPI_SHADER_IDX_FORMAT, shader->regs.ngg.spi_shader_idx_format, shader->regs.spi_shader_pos_format); - gfx12_opt_set_context_reg(R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP, RADV_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP, + gfx12_opt_set_context_reg(R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP, AC_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP, shader->regs.ngg.ge_max_output_per_subgroup); - gfx12_opt_set_context_reg(R_028B4C_GE_NGG_SUBGRP_CNTL, RADV_TRACKED_GE_NGG_SUBGRP_CNTL, + gfx12_opt_set_context_reg(R_028B4C_GE_NGG_SUBGRP_CNTL, AC_TRACKED_GE_NGG_SUBGRP_CNTL, shader->regs.ngg.ge_ngg_subgrp_cntl); gfx12_end_context_regs(); radeon_end(); } else if (pdev->info.has_set_context_pairs_packed) { radeon_begin(cs); gfx11_begin_packed_context_regs(); - gfx11_opt_set_context_reg(R_02881C_PA_CL_VS_OUT_CNTL, RADV_TRACKED_PA_CL_VS_OUT_CNTL, + gfx11_opt_set_context_reg(R_02881C_PA_CL_VS_OUT_CNTL, AC_TRACKED_PA_CL_VS_OUT_CNTL, shader->regs.pa_cl_vs_out_cntl); - gfx11_opt_set_context_reg(R_028B90_VGT_GS_INSTANCE_CNT, RADV_TRACKED_VGT_GS_INSTANCE_CNT, + gfx11_opt_set_context_reg(R_028B90_VGT_GS_INSTANCE_CNT, AC_TRACKED_VGT_GS_INSTANCE_CNT, shader->regs.vgt_gs_instance_cnt); - gfx11_opt_set_context_reg(R_028A84_VGT_PRIMITIVEID_EN, RADV_TRACKED_VGT_PRIMITIVEID_EN, + gfx11_opt_set_context_reg(R_028A84_VGT_PRIMITIVEID_EN, AC_TRACKED_VGT_PRIMITIVEID_EN, shader->regs.ngg.vgt_primitiveid_en | S_028A84_PRIMITIVEID_EN(es_enable_prim_id)); - gfx11_opt_set_context_reg2(R_028708_SPI_SHADER_IDX_FORMAT, RADV_TRACKED_SPI_SHADER_IDX_FORMAT, + gfx11_opt_set_context_reg2(R_028708_SPI_SHADER_IDX_FORMAT, AC_TRACKED_SPI_SHADER_IDX_FORMAT, shader->regs.ngg.spi_shader_idx_format, shader->regs.spi_shader_pos_format); - gfx11_opt_set_context_reg(R_0286C4_SPI_VS_OUT_CONFIG, RADV_TRACKED_SPI_VS_OUT_CONFIG, + gfx11_opt_set_context_reg(R_0286C4_SPI_VS_OUT_CONFIG, AC_TRACKED_SPI_VS_OUT_CONFIG, shader->regs.spi_vs_out_config); - gfx11_opt_set_context_reg(R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP, RADV_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP, + gfx11_opt_set_context_reg(R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP, AC_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP, shader->regs.ngg.ge_max_output_per_subgroup); - gfx11_opt_set_context_reg(R_028B4C_GE_NGG_SUBGRP_CNTL, RADV_TRACKED_GE_NGG_SUBGRP_CNTL, + gfx11_opt_set_context_reg(R_028B4C_GE_NGG_SUBGRP_CNTL, AC_TRACKED_GE_NGG_SUBGRP_CNTL, shader->regs.ngg.ge_ngg_subgrp_cntl); gfx11_end_packed_context_regs(); radeon_end(); } else { radeon_begin(cs); - radeon_opt_set_context_reg(R_02881C_PA_CL_VS_OUT_CNTL, RADV_TRACKED_PA_CL_VS_OUT_CNTL, + radeon_opt_set_context_reg(R_02881C_PA_CL_VS_OUT_CNTL, AC_TRACKED_PA_CL_VS_OUT_CNTL, shader->regs.pa_cl_vs_out_cntl); - radeon_opt_set_context_reg(R_028B90_VGT_GS_INSTANCE_CNT, RADV_TRACKED_VGT_GS_INSTANCE_CNT, + radeon_opt_set_context_reg(R_028B90_VGT_GS_INSTANCE_CNT, AC_TRACKED_VGT_GS_INSTANCE_CNT, shader->regs.vgt_gs_instance_cnt); - radeon_opt_set_context_reg(R_028A84_VGT_PRIMITIVEID_EN, RADV_TRACKED_VGT_PRIMITIVEID_EN, + radeon_opt_set_context_reg(R_028A84_VGT_PRIMITIVEID_EN, AC_TRACKED_VGT_PRIMITIVEID_EN, shader->regs.ngg.vgt_primitiveid_en | S_028A84_PRIMITIVEID_EN(es_enable_prim_id)); - radeon_opt_set_context_reg2(R_028708_SPI_SHADER_IDX_FORMAT, RADV_TRACKED_SPI_SHADER_IDX_FORMAT, + radeon_opt_set_context_reg2(R_028708_SPI_SHADER_IDX_FORMAT, AC_TRACKED_SPI_SHADER_IDX_FORMAT, shader->regs.ngg.spi_shader_idx_format, shader->regs.spi_shader_pos_format); - radeon_opt_set_context_reg(R_0286C4_SPI_VS_OUT_CONFIG, RADV_TRACKED_SPI_VS_OUT_CONFIG, + radeon_opt_set_context_reg(R_0286C4_SPI_VS_OUT_CONFIG, AC_TRACKED_SPI_VS_OUT_CONFIG, shader->regs.spi_vs_out_config); - radeon_opt_set_context_reg(R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP, RADV_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP, + radeon_opt_set_context_reg(R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP, AC_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP, shader->regs.ngg.ge_max_output_per_subgroup); - radeon_opt_set_context_reg(R_028B4C_GE_NGG_SUBGRP_CNTL, RADV_TRACKED_GE_NGG_SUBGRP_CNTL, + radeon_opt_set_context_reg(R_028B4C_GE_NGG_SUBGRP_CNTL, AC_TRACKED_GE_NGG_SUBGRP_CNTL, shader->regs.ngg.ge_ngg_subgrp_cntl); radeon_end(); } @@ -3143,7 +3141,7 @@ radv_emit_hw_ngg(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *e } } - radeon_opt_set_context_reg(R_028A44_VGT_GS_ONCHIP_CNTL, RADV_TRACKED_VGT_GS_ONCHIP_CNTL, + radeon_opt_set_context_reg(R_028A44_VGT_GS_ONCHIP_CNTL, AC_TRACKED_VGT_GS_ONCHIP_CNTL, shader->regs.vgt_gs_onchip_cntl); } @@ -3335,18 +3333,18 @@ radv_emit_hw_gs(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *gs radeon_begin(cs); - radeon_opt_set_context_reg3(R_028A60_VGT_GSVS_RING_OFFSET_1, RADV_TRACKED_VGT_GSVS_RING_OFFSET_1, + radeon_opt_set_context_reg3(R_028A60_VGT_GSVS_RING_OFFSET_1, AC_TRACKED_VGT_GSVS_RING_OFFSET_1, gs->regs.gs.vgt_gsvs_ring_offset[0], gs->regs.gs.vgt_gsvs_ring_offset[1], gs->regs.gs.vgt_gsvs_ring_offset[2]); - radeon_opt_set_context_reg(R_028AB0_VGT_GSVS_RING_ITEMSIZE, RADV_TRACKED_VGT_GSVS_RING_ITEMSIZE, + radeon_opt_set_context_reg(R_028AB0_VGT_GSVS_RING_ITEMSIZE, AC_TRACKED_VGT_GSVS_RING_ITEMSIZE, gs->regs.gs.vgt_gsvs_ring_itemsize); - radeon_opt_set_context_reg4(R_028B5C_VGT_GS_VERT_ITEMSIZE, RADV_TRACKED_VGT_GS_VERT_ITEMSIZE, + radeon_opt_set_context_reg4(R_028B5C_VGT_GS_VERT_ITEMSIZE, AC_TRACKED_VGT_GS_VERT_ITEMSIZE, gs->regs.gs.vgt_gs_vert_itemsize[0], gs->regs.gs.vgt_gs_vert_itemsize[1], gs->regs.gs.vgt_gs_vert_itemsize[2], gs->regs.gs.vgt_gs_vert_itemsize[3]); - radeon_opt_set_context_reg(R_028B90_VGT_GS_INSTANCE_CNT, RADV_TRACKED_VGT_GS_INSTANCE_CNT, + radeon_opt_set_context_reg(R_028B90_VGT_GS_INSTANCE_CNT, AC_TRACKED_VGT_GS_INSTANCE_CNT, gs->regs.gs.vgt_gs_instance_cnt); if (pdev->info.gfx_level >= GFX9) { @@ -3359,11 +3357,11 @@ radv_emit_hw_gs(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *gs gs_state->lds_size, pdev->info.gfx_level, MESA_SHADER_GEOMETRY))); } - radeon_opt_set_context_reg(R_028A44_VGT_GS_ONCHIP_CNTL, RADV_TRACKED_VGT_GS_ONCHIP_CNTL, + radeon_opt_set_context_reg(R_028A44_VGT_GS_ONCHIP_CNTL, AC_TRACKED_VGT_GS_ONCHIP_CNTL, gs->regs.vgt_gs_onchip_cntl); if (pdev->info.gfx_level == GFX9) { - radeon_opt_set_context_reg(R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, RADV_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP, + radeon_opt_set_context_reg(R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, AC_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs->regs.gs.vgt_gs_max_prims_per_subgroup); } } else { @@ -3376,7 +3374,7 @@ radv_emit_hw_gs(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *gs /* GFX6-8: ESGS offchip ring buffer is allocated according to VGT_ESGS_RING_ITEMSIZE. * GFX9+: Only used to set the GS input VGPRs, emulated in shaders. */ - radeon_opt_set_context_reg(R_028AAC_VGT_ESGS_RING_ITEMSIZE, RADV_TRACKED_VGT_ESGS_RING_ITEMSIZE, + radeon_opt_set_context_reg(R_028AAC_VGT_ESGS_RING_ITEMSIZE, AC_TRACKED_VGT_ESGS_RING_ITEMSIZE, gs->regs.gs.vgt_esgs_ring_itemsize); } @@ -3409,7 +3407,7 @@ radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer) radeon_begin(cs); - radeon_opt_set_context_reg(R_028B38_VGT_GS_MAX_VERT_OUT, RADV_TRACKED_VGT_GS_MAX_VERT_OUT, + radeon_opt_set_context_reg(R_028B38_VGT_GS_MAX_VERT_OUT, AC_TRACKED_VGT_GS_MAX_VERT_OUT, gs->regs.vgt_gs_max_vert_out); if (gs->info.merged_shader_compiled_separately) { @@ -3433,8 +3431,7 @@ radv_emit_vgt_gs_out(struct radv_cmd_buffer *cmd_buffer, uint32_t vgt_gs_out_pri if (pdev->info.gfx_level >= GFX11) { radeon_set_uconfig_reg(R_030998_VGT_GS_OUT_PRIM_TYPE, vgt_gs_out_prim_type); } else { - radeon_opt_set_context_reg(R_028A6C_VGT_GS_OUT_PRIM_TYPE, RADV_TRACKED_VGT_GS_OUT_PRIM_TYPE, - vgt_gs_out_prim_type); + radeon_opt_set_context_reg(R_028A6C_VGT_GS_OUT_PRIM_TYPE, AC_TRACKED_VGT_GS_OUT_PRIM_TYPE, vgt_gs_out_prim_type); } radeon_end(); } @@ -3474,7 +3471,7 @@ radv_emit_mesh_shader(struct radv_cmd_buffer *cmd_buffer) radeon_begin(cs); - radeon_opt_set_context_reg(R_028B38_VGT_GS_MAX_VERT_OUT, RADV_TRACKED_VGT_GS_MAX_VERT_OUT, + radeon_opt_set_context_reg(R_028B38_VGT_GS_MAX_VERT_OUT, AC_TRACKED_VGT_GS_MAX_VERT_OUT, ms->regs.vgt_gs_max_vert_out); radeon_set_uconfig_reg_idx(&pdev->info, R_030908_VGT_PRIMITIVE_TYPE, 1, V_008958_DI_PT_POINTLIST); radeon_end(); @@ -3623,7 +3620,7 @@ radv_emit_ps_inputs(struct radv_cmd_buffer *cmd_buffer) * These are only exactly known here so couldn't be precomputed. */ const unsigned num_per_vertex_params = ps->info.ps.num_inputs - num_per_primitive_params; - radeon_opt_set_context_reg(R_0286D8_SPI_PS_IN_CONTROL, RADV_TRACKED_SPI_PS_IN_CONTROL, + radeon_opt_set_context_reg(R_0286D8_SPI_PS_IN_CONTROL, AC_TRACKED_SPI_PS_IN_CONTROL, ps->regs.ps.spi_ps_in_control | S_0286D8_NUM_INTERP(num_per_vertex_params) | S_0286D8_NUM_PRIM_INTERP(num_per_primitive_params)); } @@ -3650,31 +3647,31 @@ radv_emit_fragment_shader_state(struct radv_cmd_buffer *cmd_buffer, const struct const uint32_t pa_sc_hisz_control = ps ? ps->regs.ps.pa_sc_hisz_control : 0; gfx12_begin_context_regs(); - gfx12_opt_set_context_reg2(R_02865C_SPI_PS_INPUT_ENA, RADV_TRACKED_SPI_PS_INPUT_ENA, spi_ps_input_ena, + gfx12_opt_set_context_reg2(R_02865C_SPI_PS_INPUT_ENA, AC_TRACKED_SPI_PS_INPUT_ENA, spi_ps_input_ena, spi_ps_input_addr); - gfx12_opt_set_context_reg(R_028640_SPI_PS_IN_CONTROL, RADV_TRACKED_SPI_PS_IN_CONTROL, spi_ps_in_control); + gfx12_opt_set_context_reg(R_028640_SPI_PS_IN_CONTROL, AC_TRACKED_SPI_PS_IN_CONTROL, spi_ps_in_control); - gfx12_opt_set_context_reg(R_028BBC_PA_SC_HISZ_CONTROL, RADV_TRACKED_PA_SC_HISZ_CONTROL, pa_sc_hisz_control); + gfx12_opt_set_context_reg(R_028BBC_PA_SC_HISZ_CONTROL, AC_TRACKED_PA_SC_HISZ_CONTROL, pa_sc_hisz_control); gfx12_end_context_regs(); } else if (pdev->info.has_set_context_pairs_packed) { gfx11_begin_packed_context_regs(); - gfx11_opt_set_context_reg2(R_0286CC_SPI_PS_INPUT_ENA, RADV_TRACKED_SPI_PS_INPUT_ENA, spi_ps_input_ena, + gfx11_opt_set_context_reg2(R_0286CC_SPI_PS_INPUT_ENA, AC_TRACKED_SPI_PS_INPUT_ENA, spi_ps_input_ena, spi_ps_input_addr); - gfx11_opt_set_context_reg(R_0286D8_SPI_PS_IN_CONTROL, RADV_TRACKED_SPI_PS_IN_CONTROL, spi_ps_in_control); + gfx11_opt_set_context_reg(R_0286D8_SPI_PS_IN_CONTROL, AC_TRACKED_SPI_PS_IN_CONTROL, spi_ps_in_control); gfx11_end_packed_context_regs(); } else { const uint32_t pa_sc_shader_control = ps ? ps->regs.ps.pa_sc_shader_control : 0; - radeon_opt_set_context_reg2(R_0286CC_SPI_PS_INPUT_ENA, RADV_TRACKED_SPI_PS_INPUT_ENA, spi_ps_input_ena, + radeon_opt_set_context_reg2(R_0286CC_SPI_PS_INPUT_ENA, AC_TRACKED_SPI_PS_INPUT_ENA, spi_ps_input_ena, spi_ps_input_addr); if (pdev->info.gfx_level != GFX10_3) { - radeon_opt_set_context_reg(R_0286D8_SPI_PS_IN_CONTROL, RADV_TRACKED_SPI_PS_IN_CONTROL, spi_ps_in_control); + radeon_opt_set_context_reg(R_0286D8_SPI_PS_IN_CONTROL, AC_TRACKED_SPI_PS_IN_CONTROL, spi_ps_in_control); } if (pdev->info.gfx_level >= GFX9 && pdev->info.gfx_level < GFX11) - radeon_opt_set_context_reg(R_028C40_PA_SC_SHADER_CONTROL, RADV_TRACKED_PA_SC_SHADER_CONTROL, + radeon_opt_set_context_reg(R_028C40_PA_SC_SHADER_CONTROL, AC_TRACKED_PA_SC_SHADER_CONTROL, pa_sc_shader_control); } radeon_end(); @@ -3733,7 +3730,7 @@ radv_emit_vgt_reuse(struct radv_cmd_buffer *cmd_buffer, const struct radv_vgt_sh const bool has_legacy_tess_gs = key->tess && key->gs && !key->ngg; radeon_begin(cs); - radeon_opt_set_context_reg(R_028AB4_VGT_REUSE_OFF, RADV_TRACKED_VGT_REUSE_OFF, + radeon_opt_set_context_reg(R_028AB4_VGT_REUSE_OFF, AC_TRACKED_VGT_REUSE_OFF, S_028AB4_REUSE_OFF(has_legacy_tess_gs)); radeon_end(); } @@ -3745,7 +3742,7 @@ radv_emit_vgt_reuse(struct radv_cmd_buffer *cmd_buffer, const struct radv_vgt_sh } radeon_begin(cs); - radeon_opt_set_context_reg(R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, RADV_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL, + radeon_opt_set_context_reg(R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, AC_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL, S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth)); radeon_end(); } @@ -3765,7 +3762,7 @@ radv_emit_vgt_shader_config_gfx12(struct radv_cmd_buffer *cmd_buffer, const stru stages |= S_028A98_HS_EN(1) | S_028A98_HS_W32_EN(key->hs_wave32); radeon_begin(cs); - radeon_opt_set_context_reg(R_028A98_VGT_SHADER_STAGES_EN, RADV_TRACKED_VGT_SHADER_STAGES_EN, stages); + radeon_opt_set_context_reg(R_028A98_VGT_SHADER_STAGES_EN, AC_TRACKED_VGT_SHADER_STAGES_EN, stages); radeon_end(); } @@ -3817,7 +3814,7 @@ radv_emit_vgt_shader_config_gfx6(struct radv_cmd_buffer *cmd_buffer, const struc } radeon_begin(cs); - radeon_opt_set_context_reg(R_028B54_VGT_SHADER_STAGES_EN, RADV_TRACKED_VGT_SHADER_STAGES_EN, stages); + radeon_opt_set_context_reg(R_028B54_VGT_SHADER_STAGES_EN, AC_TRACKED_VGT_SHADER_STAGES_EN, stages); radeon_end(); } @@ -3860,10 +3857,10 @@ gfx103_emit_vgt_draw_payload_cntl(struct radv_cmd_buffer *cmd_buffer) radeon_begin(cs); if (pdev->info.gfx_level >= GFX12) { - radeon_opt_set_context_reg(R_028AA0_VGT_DRAW_PAYLOAD_CNTL, RADV_TRACKED_VGT_DRAW_PAYLOAD_CNTL, + radeon_opt_set_context_reg(R_028AA0_VGT_DRAW_PAYLOAD_CNTL, AC_TRACKED_VGT_DRAW_PAYLOAD_CNTL, vgt_draw_payload_cntl); } else { - radeon_opt_set_context_reg(R_028A98_VGT_DRAW_PAYLOAD_CNTL, RADV_TRACKED_VGT_DRAW_PAYLOAD_CNTL, + radeon_opt_set_context_reg(R_028A98_VGT_DRAW_PAYLOAD_CNTL, AC_TRACKED_VGT_DRAW_PAYLOAD_CNTL, vgt_draw_payload_cntl); } @@ -3894,7 +3891,7 @@ gfx103_emit_vrs_state(struct radv_cmd_buffer *cmd_buffer) * in DX12 it's fully dynamic. */ radeon_begin(cs); - radeon_opt_set_context_reg(R_028848_PA_CL_VRS_CNTL, RADV_TRACKED_PA_CL_VRS_CNTL, + radeon_opt_set_context_reg(R_028848_PA_CL_VRS_CNTL, AC_TRACKED_PA_CL_VRS_CNTL, S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE) | S_028848_VERTEX_RATE_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE)); radeon_end(); @@ -3907,7 +3904,7 @@ gfx103_emit_vrs_state(struct radv_cmd_buffer *cmd_buffer) if (pdev->info.gfx_level < GFX11) { radeon_begin(cs); - radeon_opt_set_context_reg(R_028064_DB_VRS_OVERRIDE_CNTL, RADV_TRACKED_DB_VRS_OVERRIDE_CNTL, + radeon_opt_set_context_reg(R_028064_DB_VRS_OVERRIDE_CNTL, AC_TRACKED_DB_VRS_OVERRIDE_CNTL, S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(mode) | S_028064_VRS_OVERRIDE_RATE_X(rate_x) | S_028064_VRS_OVERRIDE_RATE_Y(rate_y)); radeon_end(); @@ -5914,9 +5911,9 @@ radv_emit_occlusion_query_state(struct radv_cmd_buffer *cmd_buffer) radeon_begin(cmd_buffer->cs); if (pdev->info.gfx_level >= GFX12) { - radeon_opt_set_context_reg(R_028060_DB_COUNT_CONTROL, RADV_TRACKED_DB_COUNT_CONTROL, db_count_control); + radeon_opt_set_context_reg(R_028060_DB_COUNT_CONTROL, AC_TRACKED_DB_COUNT_CONTROL, db_count_control); } else { - radeon_opt_set_context_reg(R_028004_DB_COUNT_CONTROL, RADV_TRACKED_DB_COUNT_CONTROL, db_count_control); + radeon_opt_set_context_reg(R_028004_DB_COUNT_CONTROL, AC_TRACKED_DB_COUNT_CONTROL, db_count_control); } radeon_end(); @@ -7224,7 +7221,7 @@ radv_emit_primitive_restart(struct radv_cmd_buffer *cmd_buffer, bool enable) if (enable && gfx_level <= GFX7) { const uint32_t primitive_reset_index = radv_get_primitive_reset_index(cmd_buffer); - radeon_opt_set_context_reg(R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, RADV_TRACKED_VGT_MULTI_PRIM_IB_RESET_INDX, + radeon_opt_set_context_reg(R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, AC_TRACKED_VGT_MULTI_PRIM_IB_RESET_INDX, primitive_reset_index); } } @@ -9875,7 +9872,7 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou primary->state.uses_draw_indirect |= secondary->state.uses_draw_indirect; - for (uint32_t reg = 0; reg < RADV_NUM_ALL_TRACKED_REGS; reg++) { + for (uint32_t reg = 0; reg < AC_NUM_ALL_TRACKED_REGS; reg++) { if (!BITSET_TEST(secondary_cs->tracked_regs.reg_saved_mask, reg)) continue; @@ -11752,9 +11749,9 @@ radv_emit_db_shader_control(struct radv_cmd_buffer *cmd_buffer) radeon_begin(cmd_buffer->cs); if (pdev->info.gfx_level >= GFX12) { - radeon_opt_set_context_reg(R_02806C_DB_SHADER_CONTROL, RADV_TRACKED_DB_SHADER_CONTROL, db_shader_control); + radeon_opt_set_context_reg(R_02806C_DB_SHADER_CONTROL, AC_TRACKED_DB_SHADER_CONTROL, db_shader_control); } else { - radeon_opt_set_context_reg(R_02880C_DB_SHADER_CONTROL, RADV_TRACKED_DB_SHADER_CONTROL, db_shader_control); + radeon_opt_set_context_reg(R_02880C_DB_SHADER_CONTROL, AC_TRACKED_DB_SHADER_CONTROL, db_shader_control); if (gpu_info->has_pops_missed_overlap_bug) radeon_set_context_reg(R_028060_DB_DFSM_CONTROL, db_dfsm_control); @@ -11833,14 +11830,13 @@ radv_emit_fragment_output_state(struct radv_cmd_buffer *cmd_buffer) gfx12_end_context_regs(); } else if (pdev->info.has_set_context_pairs_packed) { gfx11_begin_packed_context_regs(); - gfx11_opt_set_context_reg(R_02823C_CB_SHADER_MASK, RADV_TRACKED_CB_SHADER_MASK, cmd_buffer->state.cb_shader_mask); - gfx11_opt_set_context_reg2(R_028710_SPI_SHADER_Z_FORMAT, RADV_TRACKED_SPI_SHADER_Z_FORMAT, + gfx11_opt_set_context_reg(R_02823C_CB_SHADER_MASK, AC_TRACKED_CB_SHADER_MASK, cmd_buffer->state.cb_shader_mask); + gfx11_opt_set_context_reg2(R_028710_SPI_SHADER_Z_FORMAT, AC_TRACKED_SPI_SHADER_Z_FORMAT, cmd_buffer->state.spi_shader_z_format, col_format_compacted); gfx11_end_packed_context_regs(); } else { - radeon_opt_set_context_reg(R_02823C_CB_SHADER_MASK, RADV_TRACKED_CB_SHADER_MASK, - cmd_buffer->state.cb_shader_mask); - radeon_opt_set_context_reg2(R_028710_SPI_SHADER_Z_FORMAT, RADV_TRACKED_SPI_SHADER_Z_FORMAT, + radeon_opt_set_context_reg(R_02823C_CB_SHADER_MASK, AC_TRACKED_CB_SHADER_MASK, cmd_buffer->state.cb_shader_mask); + radeon_opt_set_context_reg2(R_028710_SPI_SHADER_Z_FORMAT, AC_TRACKED_SPI_SHADER_Z_FORMAT, cmd_buffer->state.spi_shader_z_format, col_format_compacted); } radeon_end(); @@ -11878,38 +11874,38 @@ radv_emit_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer) (ds.stencil.back.op.pass != ds.stencil.back.op.depth_fail)); gfx12_begin_context_regs(); - gfx12_opt_set_context_reg(R_02800C_DB_RENDER_OVERRIDE, RADV_TRACKED_DB_RENDER_OVERRIDE, + gfx12_opt_set_context_reg(R_02800C_DB_RENDER_OVERRIDE, AC_TRACKED_DB_RENDER_OVERRIDE, S_02800C_FORCE_STENCIL_READ(1) | S_02800C_FORCE_STENCIL_VALID(force_s_valid)); - gfx12_opt_set_context_reg(R_028070_DB_DEPTH_CONTROL, RADV_TRACKED_DB_DEPTH_CONTROL, db_depth_control); + gfx12_opt_set_context_reg(R_028070_DB_DEPTH_CONTROL, AC_TRACKED_DB_DEPTH_CONTROL, db_depth_control); if (ds.stencil.test_enable) { - gfx12_opt_set_context_reg(R_028074_DB_STENCIL_CONTROL, RADV_TRACKED_DB_STENCIL_CONTROL, db_stencil_control); + gfx12_opt_set_context_reg(R_028074_DB_STENCIL_CONTROL, AC_TRACKED_DB_STENCIL_CONTROL, db_stencil_control); gfx12_opt_set_context_reg( - R_028088_DB_STENCIL_REF, RADV_TRACKED_DB_STENCIL_REF, + R_028088_DB_STENCIL_REF, AC_TRACKED_DB_STENCIL_REF, S_028088_TESTVAL(ds.stencil.front.reference) | S_028088_TESTVAL_BF(ds.stencil.back.reference)); gfx12_opt_set_context_reg2( - R_028090_DB_STENCIL_READ_MASK, RADV_TRACKED_DB_STENCIL_READ_MASK, + R_028090_DB_STENCIL_READ_MASK, AC_TRACKED_DB_STENCIL_READ_MASK, S_028090_TESTMASK(ds.stencil.front.compare_mask) | S_028090_TESTMASK_BF(ds.stencil.back.compare_mask), S_028094_WRITEMASK(ds.stencil.front.write_mask) | S_028094_WRITEMASK_BF(ds.stencil.back.write_mask)); } if (ds.depth.bounds_test.enable) { - gfx12_opt_set_context_reg2(R_028050_DB_DEPTH_BOUNDS_MIN, RADV_TRACKED_DB_DEPTH_BOUNDS_MIN, depth_bounds_min, + gfx12_opt_set_context_reg2(R_028050_DB_DEPTH_BOUNDS_MIN, AC_TRACKED_DB_DEPTH_BOUNDS_MIN, depth_bounds_min, depth_bounds_max); } gfx12_end_context_regs(); } else if (pdev->info.has_set_context_pairs_packed) { gfx11_begin_packed_context_regs(); - gfx11_opt_set_context_reg(R_028800_DB_DEPTH_CONTROL, RADV_TRACKED_DB_DEPTH_CONTROL, db_depth_control); + gfx11_opt_set_context_reg(R_028800_DB_DEPTH_CONTROL, AC_TRACKED_DB_DEPTH_CONTROL, db_depth_control); if (ds.stencil.test_enable) { - gfx11_opt_set_context_reg(R_02842C_DB_STENCIL_CONTROL, RADV_TRACKED_DB_STENCIL_CONTROL, db_stencil_control); + gfx11_opt_set_context_reg(R_02842C_DB_STENCIL_CONTROL, AC_TRACKED_DB_STENCIL_CONTROL, db_stencil_control); gfx11_opt_set_context_reg2( - R_028430_DB_STENCILREFMASK, RADV_TRACKED_DB_STENCILREFMASK, + R_028430_DB_STENCILREFMASK, AC_TRACKED_DB_STENCILREFMASK, S_028430_STENCILTESTVAL(ds.stencil.front.reference) | S_028430_STENCILMASK(ds.stencil.front.compare_mask) | S_028430_STENCILWRITEMASK(ds.stencil.front.write_mask) | S_028430_STENCILOPVAL(1), S_028434_STENCILTESTVAL_BF(ds.stencil.back.reference) | @@ -11918,18 +11914,18 @@ radv_emit_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer) } if (ds.depth.bounds_test.enable) { - gfx11_opt_set_context_reg2(R_028020_DB_DEPTH_BOUNDS_MIN, RADV_TRACKED_DB_DEPTH_BOUNDS_MIN, depth_bounds_min, + gfx11_opt_set_context_reg2(R_028020_DB_DEPTH_BOUNDS_MIN, AC_TRACKED_DB_DEPTH_BOUNDS_MIN, depth_bounds_min, depth_bounds_max); } gfx11_end_packed_context_regs(); } else { - radeon_opt_set_context_reg(R_028800_DB_DEPTH_CONTROL, RADV_TRACKED_DB_DEPTH_CONTROL, db_depth_control); + radeon_opt_set_context_reg(R_028800_DB_DEPTH_CONTROL, AC_TRACKED_DB_DEPTH_CONTROL, db_depth_control); if (ds.stencil.test_enable) { - radeon_opt_set_context_reg(R_02842C_DB_STENCIL_CONTROL, RADV_TRACKED_DB_STENCIL_CONTROL, db_stencil_control); + radeon_opt_set_context_reg(R_02842C_DB_STENCIL_CONTROL, AC_TRACKED_DB_STENCIL_CONTROL, db_stencil_control); radeon_opt_set_context_reg2( - R_028430_DB_STENCILREFMASK, RADV_TRACKED_DB_STENCILREFMASK, + R_028430_DB_STENCILREFMASK, AC_TRACKED_DB_STENCILREFMASK, S_028430_STENCILTESTVAL(ds.stencil.front.reference) | S_028430_STENCILMASK(ds.stencil.front.compare_mask) | S_028430_STENCILWRITEMASK(ds.stencil.front.write_mask) | S_028430_STENCILOPVAL(1), S_028434_STENCILTESTVAL_BF(ds.stencil.back.reference) | @@ -11938,7 +11934,7 @@ radv_emit_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer) } if (ds.depth.bounds_test.enable) { - radeon_opt_set_context_reg2(R_028020_DB_DEPTH_BOUNDS_MIN, RADV_TRACKED_DB_DEPTH_BOUNDS_MIN, depth_bounds_min, + radeon_opt_set_context_reg2(R_028020_DB_DEPTH_BOUNDS_MIN, AC_TRACKED_DB_DEPTH_BOUNDS_MIN, depth_bounds_min, depth_bounds_max); } } @@ -11989,58 +11985,58 @@ radv_emit_raster_state(struct radv_cmd_buffer *cmd_buffer) radeon_begin(cmd_buffer->cs); if (pdev->info.gfx_level >= GFX12) { gfx12_begin_context_regs(); - gfx12_opt_set_context_reg(R_028A08_PA_SU_LINE_CNTL, RADV_TRACKED_PA_SU_LINE_CNTL, pa_su_line_cntl); + gfx12_opt_set_context_reg(R_028A08_PA_SU_LINE_CNTL, AC_TRACKED_PA_SU_LINE_CNTL, pa_su_line_cntl); - gfx12_opt_set_context_reg(R_028A0C_PA_SC_LINE_STIPPLE, RADV_TRACKED_PA_SC_LINE_STIPPLE, + gfx12_opt_set_context_reg(R_028A0C_PA_SC_LINE_STIPPLE, AC_TRACKED_PA_SC_LINE_STIPPLE, S_028A0C_LINE_PATTERN(d->vk.rs.line.stipple.pattern) | S_028A0C_REPEAT_COUNT(d->vk.rs.line.stipple.factor - 1)); - gfx12_opt_set_context_reg(R_028BDC_PA_SC_LINE_CNTL, RADV_TRACKED_PA_SC_LINE_CNTL, pa_sc_line_cntl); + gfx12_opt_set_context_reg(R_028BDC_PA_SC_LINE_CNTL, AC_TRACKED_PA_SC_LINE_CNTL, pa_sc_line_cntl); gfx12_opt_set_context_reg( - R_028810_PA_CL_CLIP_CNTL, RADV_TRACKED_PA_CL_CLIP_CNTL, + R_028810_PA_CL_CLIP_CNTL, AC_TRACKED_PA_CL_CLIP_CNTL, S_028810_DX_RASTERIZATION_KILL(d->vk.rs.rasterizer_discard_enable) | S_028810_ZCLIP_NEAR_DISABLE(!depth_clip_enable) | S_028810_ZCLIP_FAR_DISABLE(!depth_clip_enable) | S_028810_DX_CLIP_SPACE_DEF(!d->vk.vp.depth_clip_negative_one_to_one) | S_028810_DX_LINEAR_ATTR_CLIP_ENA(1)); - gfx12_opt_set_context_reg(R_028A44_PA_SC_LINE_STIPPLE_RESET, RADV_TRACKED_PA_SC_LINE_STIPPLE_RESET, + gfx12_opt_set_context_reg(R_028A44_PA_SC_LINE_STIPPLE_RESET, AC_TRACKED_PA_SC_LINE_STIPPLE_RESET, S_028A44_AUTO_RESET_CNTL(auto_reset_cntl)); - gfx12_opt_set_context_reg(R_02881C_PA_SU_SC_MODE_CNTL, RADV_TRACKED_PA_SU_SC_MODE_CNTL, pa_su_sc_mode_cntl); + gfx12_opt_set_context_reg(R_02881C_PA_SU_SC_MODE_CNTL, AC_TRACKED_PA_SU_SC_MODE_CNTL, pa_su_sc_mode_cntl); gfx12_end_context_regs(); } else if (pdev->info.has_set_context_pairs_packed) { gfx11_begin_packed_context_regs(); - gfx11_opt_set_context_reg(R_028A08_PA_SU_LINE_CNTL, RADV_TRACKED_PA_SU_LINE_CNTL, pa_su_line_cntl); + gfx11_opt_set_context_reg(R_028A08_PA_SU_LINE_CNTL, AC_TRACKED_PA_SU_LINE_CNTL, pa_su_line_cntl); - gfx11_opt_set_context_reg(R_028A0C_PA_SC_LINE_STIPPLE, RADV_TRACKED_PA_SC_LINE_STIPPLE, + gfx11_opt_set_context_reg(R_028A0C_PA_SC_LINE_STIPPLE, AC_TRACKED_PA_SC_LINE_STIPPLE, S_028A0C_LINE_PATTERN(d->vk.rs.line.stipple.pattern) | S_028A0C_REPEAT_COUNT(d->vk.rs.line.stipple.factor - 1) | S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl)); - gfx11_opt_set_context_reg(R_028BDC_PA_SC_LINE_CNTL, RADV_TRACKED_PA_SC_LINE_CNTL, pa_sc_line_cntl); + gfx11_opt_set_context_reg(R_028BDC_PA_SC_LINE_CNTL, AC_TRACKED_PA_SC_LINE_CNTL, pa_sc_line_cntl); gfx11_opt_set_context_reg( - R_028810_PA_CL_CLIP_CNTL, RADV_TRACKED_PA_CL_CLIP_CNTL, + R_028810_PA_CL_CLIP_CNTL, AC_TRACKED_PA_CL_CLIP_CNTL, S_028810_DX_RASTERIZATION_KILL(d->vk.rs.rasterizer_discard_enable) | S_028810_ZCLIP_NEAR_DISABLE(!depth_clip_enable) | S_028810_ZCLIP_FAR_DISABLE(!depth_clip_enable) | S_028810_DX_CLIP_SPACE_DEF(!d->vk.vp.depth_clip_negative_one_to_one) | S_028810_DX_LINEAR_ATTR_CLIP_ENA(1)); - gfx11_opt_set_context_reg(R_028814_PA_SU_SC_MODE_CNTL, RADV_TRACKED_PA_SU_SC_MODE_CNTL, pa_su_sc_mode_cntl); + gfx11_opt_set_context_reg(R_028814_PA_SU_SC_MODE_CNTL, AC_TRACKED_PA_SU_SC_MODE_CNTL, pa_su_sc_mode_cntl); gfx11_end_packed_context_regs(); } else { - radeon_opt_set_context_reg(R_028A08_PA_SU_LINE_CNTL, RADV_TRACKED_PA_SU_LINE_CNTL, pa_su_line_cntl); + radeon_opt_set_context_reg(R_028A08_PA_SU_LINE_CNTL, AC_TRACKED_PA_SU_LINE_CNTL, pa_su_line_cntl); - radeon_opt_set_context_reg(R_028A0C_PA_SC_LINE_STIPPLE, RADV_TRACKED_PA_SC_LINE_STIPPLE, + radeon_opt_set_context_reg(R_028A0C_PA_SC_LINE_STIPPLE, AC_TRACKED_PA_SC_LINE_STIPPLE, S_028A0C_LINE_PATTERN(d->vk.rs.line.stipple.pattern) | S_028A0C_REPEAT_COUNT(d->vk.rs.line.stipple.factor - 1) | S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl)); - radeon_opt_set_context_reg(R_028BDC_PA_SC_LINE_CNTL, RADV_TRACKED_PA_SC_LINE_CNTL, pa_sc_line_cntl); + radeon_opt_set_context_reg(R_028BDC_PA_SC_LINE_CNTL, AC_TRACKED_PA_SC_LINE_CNTL, pa_sc_line_cntl); radeon_opt_set_context_reg( - R_028810_PA_CL_CLIP_CNTL, RADV_TRACKED_PA_CL_CLIP_CNTL, + R_028810_PA_CL_CLIP_CNTL, AC_TRACKED_PA_CL_CLIP_CNTL, S_028810_DX_RASTERIZATION_KILL(d->vk.rs.rasterizer_discard_enable) | S_028810_ZCLIP_NEAR_DISABLE(!depth_clip_enable) | S_028810_ZCLIP_FAR_DISABLE(!depth_clip_enable) | S_028810_DX_CLIP_SPACE_DEF(!d->vk.vp.depth_clip_negative_one_to_one) | S_028810_DX_LINEAR_ATTR_CLIP_ENA(1)); - radeon_opt_set_context_reg(R_028814_PA_SU_SC_MODE_CNTL, RADV_TRACKED_PA_SU_SC_MODE_CNTL, pa_su_sc_mode_cntl); + radeon_opt_set_context_reg(R_028814_PA_SU_SC_MODE_CNTL, AC_TRACKED_PA_SU_SC_MODE_CNTL, pa_su_sc_mode_cntl); } radeon_end(); } @@ -12138,11 +12134,11 @@ radv_emit_cb_render_state(struct radv_cmd_buffer *cmd_buffer) } if (pdev->info.gfx_level >= GFX12) { - radeon_opt_set_context_reg(R_028850_CB_TARGET_MASK, RADV_TRACKED_CB_TARGET_MASK, cb_target_mask); - radeon_opt_set_context_reg(R_028858_CB_COLOR_CONTROL, RADV_TRACKED_CB_COLOR_CONTROL, cb_color_control); + radeon_opt_set_context_reg(R_028850_CB_TARGET_MASK, AC_TRACKED_CB_TARGET_MASK, cb_target_mask); + radeon_opt_set_context_reg(R_028858_CB_COLOR_CONTROL, AC_TRACKED_CB_COLOR_CONTROL, cb_color_control); } else { - radeon_opt_set_context_reg(R_028238_CB_TARGET_MASK, RADV_TRACKED_CB_TARGET_MASK, cb_target_mask); - radeon_opt_set_context_reg(R_028808_CB_COLOR_CONTROL, RADV_TRACKED_CB_COLOR_CONTROL, cb_color_control); + radeon_opt_set_context_reg(R_028238_CB_TARGET_MASK, AC_TRACKED_CB_TARGET_MASK, cb_target_mask); + radeon_opt_set_context_reg(R_028808_CB_COLOR_CONTROL, AC_TRACKED_CB_COLOR_CONTROL, cb_color_control); } radeon_end(); } @@ -12264,48 +12260,48 @@ radv_emit_msaa_state(struct radv_cmd_buffer *cmd_buffer) radeon_begin(cmd_buffer->cs); if (pdev->info.gfx_level >= GFX12) { gfx12_begin_context_regs(); - gfx12_opt_set_context_reg2(R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, RADV_TRACKED_PA_SC_AA_MASK_X0Y0_X1Y0, sample_mask, + gfx12_opt_set_context_reg2(R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, AC_TRACKED_PA_SC_AA_MASK_X0Y0_X1Y0, sample_mask, sample_mask); - gfx12_opt_set_context_reg(R_028BE0_PA_SC_AA_CONFIG, RADV_TRACKED_PA_SC_AA_CONFIG, pa_sc_aa_config); + gfx12_opt_set_context_reg(R_028BE0_PA_SC_AA_CONFIG, AC_TRACKED_PA_SC_AA_CONFIG, pa_sc_aa_config); gfx12_opt_set_context_reg( - R_028A48_PA_SC_MODE_CNTL_0, RADV_TRACKED_PA_SC_MODE_CNTL_0, + R_028A48_PA_SC_MODE_CNTL_0, AC_TRACKED_PA_SC_MODE_CNTL_0, S_028A48_ALTERNATE_RBS_PER_TILE(pdev->info.gfx_level >= GFX9) | S_028A48_VPORT_SCISSOR_ENABLE(1) | S_028A48_LINE_STIPPLE_ENABLE(d->vk.rs.line.stipple.enable) | S_028A48_MSAA_ENABLE(msaa_enable)); - gfx12_opt_set_context_reg(R_02807C_DB_ALPHA_TO_MASK, RADV_TRACKED_DB_ALPHA_TO_MASK, db_alpha_to_mask); - gfx12_opt_set_context_reg(R_028C5C_PA_SC_SAMPLE_PROPERTIES, RADV_TRACKED_PA_SC_SAMPLE_PROPERTIES, + gfx12_opt_set_context_reg(R_02807C_DB_ALPHA_TO_MASK, AC_TRACKED_DB_ALPHA_TO_MASK, db_alpha_to_mask); + gfx12_opt_set_context_reg(R_028C5C_PA_SC_SAMPLE_PROPERTIES, AC_TRACKED_PA_SC_SAMPLE_PROPERTIES, S_028C5C_MAX_SAMPLE_DIST(max_sample_dist)); - gfx12_opt_set_context_reg(R_028078_DB_EQAA, RADV_TRACKED_DB_EQAA, db_eqaa); + gfx12_opt_set_context_reg(R_028078_DB_EQAA, AC_TRACKED_DB_EQAA, db_eqaa); gfx12_opt_set_context_reg(R_028C54_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, - RADV_TRACKED_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, pa_sc_conservative_rast); + AC_TRACKED_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, pa_sc_conservative_rast); gfx12_end_context_regs(); } else if (pdev->info.has_set_context_pairs_packed) { gfx11_begin_packed_context_regs(); - gfx11_opt_set_context_reg2(R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, RADV_TRACKED_PA_SC_AA_MASK_X0Y0_X1Y0, sample_mask, + gfx11_opt_set_context_reg2(R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, AC_TRACKED_PA_SC_AA_MASK_X0Y0_X1Y0, sample_mask, sample_mask); - gfx11_opt_set_context_reg(R_028BE0_PA_SC_AA_CONFIG, RADV_TRACKED_PA_SC_AA_CONFIG, pa_sc_aa_config); + gfx11_opt_set_context_reg(R_028BE0_PA_SC_AA_CONFIG, AC_TRACKED_PA_SC_AA_CONFIG, pa_sc_aa_config); gfx11_opt_set_context_reg( - R_028A48_PA_SC_MODE_CNTL_0, RADV_TRACKED_PA_SC_MODE_CNTL_0, + R_028A48_PA_SC_MODE_CNTL_0, AC_TRACKED_PA_SC_MODE_CNTL_0, S_028A48_ALTERNATE_RBS_PER_TILE(pdev->info.gfx_level >= GFX9) | S_028A48_VPORT_SCISSOR_ENABLE(1) | S_028A48_LINE_STIPPLE_ENABLE(d->vk.rs.line.stipple.enable) | S_028A48_MSAA_ENABLE(msaa_enable)); - gfx11_opt_set_context_reg(R_028B70_DB_ALPHA_TO_MASK, RADV_TRACKED_DB_ALPHA_TO_MASK, db_alpha_to_mask); - gfx11_opt_set_context_reg(R_028804_DB_EQAA, RADV_TRACKED_DB_EQAA, db_eqaa); + gfx11_opt_set_context_reg(R_028B70_DB_ALPHA_TO_MASK, AC_TRACKED_DB_ALPHA_TO_MASK, db_alpha_to_mask); + gfx11_opt_set_context_reg(R_028804_DB_EQAA, AC_TRACKED_DB_EQAA, db_eqaa); gfx11_opt_set_context_reg(R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, - RADV_TRACKED_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, pa_sc_conservative_rast); + AC_TRACKED_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, pa_sc_conservative_rast); gfx11_end_packed_context_regs(); } else { - radeon_opt_set_context_reg2(R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, RADV_TRACKED_PA_SC_AA_MASK_X0Y0_X1Y0, sample_mask, + radeon_opt_set_context_reg2(R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, AC_TRACKED_PA_SC_AA_MASK_X0Y0_X1Y0, sample_mask, sample_mask); - radeon_opt_set_context_reg(R_028BE0_PA_SC_AA_CONFIG, RADV_TRACKED_PA_SC_AA_CONFIG, pa_sc_aa_config); + radeon_opt_set_context_reg(R_028BE0_PA_SC_AA_CONFIG, AC_TRACKED_PA_SC_AA_CONFIG, pa_sc_aa_config); radeon_opt_set_context_reg( - R_028A48_PA_SC_MODE_CNTL_0, RADV_TRACKED_PA_SC_MODE_CNTL_0, + R_028A48_PA_SC_MODE_CNTL_0, AC_TRACKED_PA_SC_MODE_CNTL_0, S_028A48_ALTERNATE_RBS_PER_TILE(pdev->info.gfx_level >= GFX9) | S_028A48_VPORT_SCISSOR_ENABLE(1) | S_028A48_LINE_STIPPLE_ENABLE(d->vk.rs.line.stipple.enable) | S_028A48_MSAA_ENABLE(msaa_enable)); - radeon_opt_set_context_reg(R_028B70_DB_ALPHA_TO_MASK, RADV_TRACKED_DB_ALPHA_TO_MASK, db_alpha_to_mask); - radeon_opt_set_context_reg(R_028804_DB_EQAA, RADV_TRACKED_DB_EQAA, db_eqaa); + radeon_opt_set_context_reg(R_028B70_DB_ALPHA_TO_MASK, AC_TRACKED_DB_ALPHA_TO_MASK, db_alpha_to_mask); + radeon_opt_set_context_reg(R_028804_DB_EQAA, AC_TRACKED_DB_EQAA, db_eqaa); if (pdev->info.gfx_level >= GFX9) radeon_opt_set_context_reg(R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, - RADV_TRACKED_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, pa_sc_conservative_rast); + AC_TRACKED_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, pa_sc_conservative_rast); } radeon_end(); } diff --git a/src/amd/vulkan/radv_cmd_buffer.h b/src/amd/vulkan/radv_cmd_buffer.h index fb0adc10fb8..eb7c2681b3a 100644 --- a/src/amd/vulkan/radv_cmd_buffer.h +++ b/src/amd/vulkan/radv_cmd_buffer.h @@ -279,115 +279,9 @@ enum rgp_flush_bits { RGP_FLUSH_INVAL_L1 = 0x8000, }; -enum radv_tracked_reg { - RADV_TRACKED_DB_COUNT_CONTROL, - RADV_TRACKED_DB_SHADER_CONTROL, - RADV_TRACKED_DB_VRS_OVERRIDE_CNTL, - - /* 2 consecutive registers */ - RADV_TRACKED_DB_DEPTH_BOUNDS_MIN, - RADV_TRACKED_DB_DEPTH_BOUNDS_MAX, - - /* 2 consecutive registers */ - RADV_TRACKED_DB_STENCILREFMASK, /* GFX6-11.5 */ - RADV_TRACKED_DB_STENCILREFMASK_BF, /* GFX6-11.5 */ - - /* 2 consecutive registers */ - RADV_TRACKED_DB_STENCIL_READ_MASK, /* GFX12 */ - RADV_TRACKED_DB_STENCIL_WRITE_MASK, /* GFX12 */ - - RADV_TRACKED_DB_DEPTH_CONTROL, - RADV_TRACKED_DB_STENCIL_CONTROL, - RADV_TRACKED_DB_STENCIL_REF, /* GFX12 */ - - RADV_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP, - RADV_TRACKED_GE_NGG_SUBGRP_CNTL, - - RADV_TRACKED_PA_CL_CLIP_CNTL, - RADV_TRACKED_PA_CL_VRS_CNTL, - RADV_TRACKED_PA_CL_VS_OUT_CNTL, - - RADV_TRACKED_PA_SC_BINNER_CNTL_0, - RADV_TRACKED_PA_SC_SHADER_CONTROL, - RADV_TRACKED_PA_SC_HISZ_CONTROL = RADV_TRACKED_PA_SC_SHADER_CONTROL, /* GFX12 (slot reused) */ - RADV_TRACKED_PA_SC_LINE_CNTL, - RADV_TRACKED_PA_SC_LINE_STIPPLE, - RADV_TRACKED_PA_SC_LINE_STIPPLE_RESET, /* GFX12 */ - - /* 2 consecutive registers */ - RADV_TRACKED_SPI_PS_INPUT_ENA, - RADV_TRACKED_SPI_PS_INPUT_ADDR, - - RADV_TRACKED_SPI_PS_IN_CONTROL, - - /* 2 consecutive registers */ - RADV_TRACKED_SPI_SHADER_IDX_FORMAT, - RADV_TRACKED_SPI_SHADER_POS_FORMAT, - - RADV_TRACKED_SPI_VS_OUT_CONFIG, - - /* 3 consecutive registers */ - RADV_TRACKED_SX_PS_DOWNCONVERT, - RADV_TRACKED_SX_BLEND_OPT_EPSILON, - RADV_TRACKED_SX_BLEND_OPT_CONTROL, - - RADV_TRACKED_VGT_DRAW_PAYLOAD_CNTL, - RADV_TRACKED_VGT_ESGS_RING_ITEMSIZE, /* GFX6-8 */ - RADV_TRACKED_VGT_GS_MODE, - RADV_TRACKED_VGT_GS_INSTANCE_CNT, - RADV_TRACKED_VGT_GS_ONCHIP_CNTL, - RADV_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP, - RADV_TRACKED_VGT_GS_MAX_VERT_OUT, - RADV_TRACKED_VGT_GS_OUT_PRIM_TYPE, - - /* 4 consecutive registers */ - RADV_TRACKED_VGT_GS_VERT_ITEMSIZE, - RADV_TRACKED_VGT_GS_VERT_ITEMSIZE_1, - RADV_TRACKED_VGT_GS_VERT_ITEMSIZE_2, - RADV_TRACKED_VGT_GS_VERT_ITEMSIZE_3, - - RADV_TRACKED_VGT_GSVS_RING_ITEMSIZE, - - /* 3 consecutive registers */ - RADV_TRACKED_VGT_GSVS_RING_OFFSET_1, - RADV_TRACKED_VGT_GSVS_RING_OFFSET_2, - RADV_TRACKED_VGT_GSVS_RING_OFFSET_3, - - RADV_TRACKED_VGT_MULTI_PRIM_IB_RESET_INDX, /* GFX6-7 */ - RADV_TRACKED_VGT_PRIMITIVEID_EN, - RADV_TRACKED_VGT_REUSE_OFF, - RADV_TRACKED_VGT_SHADER_STAGES_EN, - RADV_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL, - - RADV_TRACKED_PA_SU_LINE_CNTL, - RADV_TRACKED_PA_SU_SC_MODE_CNTL, - - /* 2 consecutive registers */ - RADV_TRACKED_PA_SC_AA_MASK_X0Y0_X1Y0, - - RADV_TRACKED_DB_EQAA, - RADV_TRACKED_DB_ALPHA_TO_MASK, - RADV_TRACKED_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, /* GFX9+ */ - RADV_TRACKED_PA_SC_AA_CONFIG, - RADV_TRACKED_PA_SC_MODE_CNTL_0, - RADV_TRACKED_PA_SC_SAMPLE_PROPERTIES, /* GFX12+ */ - - RADV_TRACKED_DB_RENDER_OVERRIDE, /* GFX12+ */ - - /* 2 consecutive registers */ - RADV_TRACKED_SPI_SHADER_Z_FORMAT, - RADV_TRACKED_SPI_SHADER_COL_FORMAT, - - RADV_TRACKED_CB_TARGET_MASK, - RADV_TRACKED_CB_COLOR_CONTROL, - RADV_TRACKED_CB_SHADER_MASK, - - RADV_NUM_ALL_TRACKED_REGS, -}; - struct radv_tracked_regs { - BITSET_DECLARE(reg_saved_mask, RADV_NUM_ALL_TRACKED_REGS); - uint32_t reg_value[RADV_NUM_ALL_TRACKED_REGS]; + BITSET_DECLARE(reg_saved_mask, AC_NUM_ALL_TRACKED_REGS); + uint32_t reg_value[AC_NUM_ALL_TRACKED_REGS]; uint32_t spi_ps_input_cntl[32]; uint32_t cb_blend_control[MAX_RTS]; uint32_t sx_mrt_blend_opt[MAX_RTS]; diff --git a/src/amd/vulkan/radv_cs.c b/src/amd/vulkan/radv_cs.c index db899a89ce9..5f3a64605e4 100644 --- a/src/amd/vulkan/radv_cs.c +++ b/src/amd/vulkan/radv_cs.c @@ -451,7 +451,7 @@ radv_init_tracked_regs(struct radv_cmd_stream *cs) struct radv_tracked_regs *tracked_regs = &cs->tracked_regs; /* Mark all registers as unknown. */ - memset(tracked_regs->reg_value, 0, RADV_NUM_ALL_TRACKED_REGS * sizeof(uint32_t)); + memset(tracked_regs->reg_value, 0, AC_NUM_ALL_TRACKED_REGS * sizeof(uint32_t)); BITSET_ZERO(tracked_regs->reg_saved_mask); /* 0xffffffff is an impossible value for these registers */