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anv: add required PC for Wa_14014966230

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Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25671>
This commit is contained in:
Tapani Pälli 2023-08-31 10:48:26 +03:00 • committed by Marge Bot
parent 2254eaa3ae
commit c945e0777d
1 changed files with 13 additions and 0 deletions
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13
src/intel/vulkan/genX_cmd_buffer.c
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@ -2853,6 +2853,19 @@ genX(batch_emit_pipe_control_write)(struct anv_batch *batch,
{
/* XXX - insert all workarounds and GFX specific things below. */
/* Wa_14014966230: For COMPUTE Workload - Any PIPE_CONTROL command with
* POST_SYNC Operation Enabled MUST be preceded by a PIPE_CONTROL
* with CS_STALL Bit set (with No POST_SYNC ENABLED)
*/
if (intel_device_info_is_adln(devinfo) &&
current_pipeline == GPGPU &&
post_sync_op != NoWrite) {
anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe) {
pipe.CommandStreamerStallEnable = true;
anv_debug_dump_pc(pipe, "Wa_14014966230");
};
}
#if INTEL_NEEDS_WA_1409600907
/* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
* be set with any PIPE_CONTROL with Depth Flush Enable bit set.