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freedreno/a6xx: move tile_mode to sampler-view CSO

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This is known when the CSO is created, so no need to patch it in later.

Also, it seems like smaller textures where the first level is small
enough to be linear, it seems like we should set linear tile mode.

See: dEQP-GLES3.functional.texture.format.unsized.rgb_unsigned_byte_3d_pot

Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark 2019-01-03 09:27:58 -05:00
parent eb625d30b7
commit c92c18c70c
2 changed files with 7 additions and 7 deletions
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7
src/gallium/drivers/freedreno/a6xx/fd6_emit.c
View file

@ -394,13 +394,8 @@ fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
static const struct fd6_pipe_sampler_view dummy_view = {};
const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
enum a6xx_tile_mode tile_mode = TILE6_LINEAR;
if (view->base.texture)
tile_mode = fd_resource(view->base.texture)->tile_mode;
OUT_RING(state, view->texconst0 |
A6XX_TEX_CONST_0_TILE_MODE(tile_mode));
OUT_RING(state, view->texconst0);
OUT_RING(state, view->texconst1);
OUT_RING(state, view->texconst2);
OUT_RING(state, view->texconst3);

7
src/gallium/drivers/freedreno/a6xx/fd6_texture.c
View file

@ -281,12 +281,17 @@ fd6_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
so->offset = cso->u.buf.offset;
} else {
unsigned miplevels;
enum a6xx_tile_mode tile_mode = TILE6_LINEAR;
lvl = fd_sampler_first_level(cso);
miplevels = fd_sampler_last_level(cso) - lvl;
layers = cso->u.tex.last_layer - cso->u.tex.first_layer + 1;
so->texconst0 |= A6XX_TEX_CONST_0_MIPLVLS(miplevels);
if (!fd_resource_level_linear(prsc, lvl))
tile_mode = fd_resource(prsc)->tile_mode;
so->texconst0 |= A6XX_TEX_CONST_0_MIPLVLS(miplevels) |
A6XX_TEX_CONST_0_TILE_MODE(tile_mode);
so->texconst1 =
A6XX_TEX_CONST_1_WIDTH(u_minify(prsc->width0, lvl)) |
A6XX_TEX_CONST_1_HEIGHT(u_minify(prsc->height0, lvl));