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i965/gen8: Don't add workaround bits to PIPE_CONTROL stalls if DC flush is set.

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According to the hardware docs a DC flush is sufficient to make
CS_STALL happy, there's no need to add STALL_AT_SCOREBOARD whenever
it's present.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg  <krh@bitplanet.net>
This commit is contained in:
Francisco Jerez 2015-09-03 17:19:10 +03:00
parent 2405b75bc9
commit c8ff045fdb
1 changed files with 3 additions and 1 deletions
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4
src/mesa/drivers/dri/i965/brw_pipe_control.c
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@ -36,6 +36,7 @@
* - Stall at Pixel Scoreboard
* - Post-Sync Operation
* - Depth Stall
* - DC Flush Enable
*
* I chose "Stall at Pixel Scoreboard" since we've used it effectively
* in the past, but the choice is fairly arbitrary.
@ -49,7 +50,8 @@ gen8_add_cs_stall_workaround_bits(uint32_t *flags)
PIPE_CONTROL_WRITE_DEPTH_COUNT |
PIPE_CONTROL_WRITE_TIMESTAMP |
PIPE_CONTROL_STALL_AT_SCOREBOARD |
PIPE_CONTROL_DEPTH_STALL;
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_DATA_CACHE_INVALIDATE;
/* If we're doing a CS stall, and don't already have one of the
* workaround bits set, add "Stall at Pixel Scoreboard."