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iris: Disable some 8bpp fast-clears within miptail
Prevents the following piglit test from failing on DG2 when Tile64 is force-enabled: fbo-clear-formats GL_ARB_texture_rg -auto -fbo Reviewed-by: Rohan Garg <rohan.garg@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38063>
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1 changed files with 24 additions and 12 deletions
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@ -128,21 +128,33 @@ can_fast_clear_color(struct iris_context *ice,
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if (!iris_is_color_fast_clear_compatible(ice, res->surf.format, color))
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return false;
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/* The RENDER_SURFACE_STATE page for TGL says:
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/* From the TGL PRM Vol. 9, "Render Target Fast Clear":
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*
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* For an 8 bpp surface with NUM_MULTISAMPLES = 1, Surface Width not
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* multiple of 64 pixels and more than 1 mip level in the view, Fast Clear
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* is not supported when AUX_CCS_E is set in this field.
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* SW needs to disable Render Target Fast clear for surface type = 2D,
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* surface format = 8 bpp, tile format = TYS pr TY, Mip is not aligned to
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* 32x4 pixels
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*
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* The granularity of a fast-clear is one CCS element. For an 8 bpp primary
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* surface, this maps to 32px x 4rows. Due to the surface layout parameters,
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* if LOD0's width isn't a multiple of 64px, LOD1 and LOD2+ will share CCS
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* elements. Assuming LOD2 exists, don't fast-clear any level above LOD0
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* to avoid stomping on other LODs.
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* This can also be found in the ACM PRMs and it seems to be applicable
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* according to test results.
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*/
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if (level > 0 && util_format_get_blocksizebits(p_res->format) == 8 &&
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p_res->width0 % 64) {
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return false;
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if (util_format_get_blocksizebits(p_res->format) == 8) {
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if (level - res->surf.miptail_start_level >= 5) {
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/* If miptails are in use, avoid using slot 5 or anything afterwards.
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* According to icl_std_y_2d_miptail_offset_el[], this slot offsets
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* 16 pixels into the miptail.
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*/
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return false;
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}
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if (level > 0 && p_res->width0 % 64 &&
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res->surf.image_alignment_el.w % 32) {
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/* The granularity of a fast-clear is one CCS element. For an 8 bpp
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* primary surface, this maps to 32px x 4rows. Due to the surface
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* layout parameters, if LOD0's width isn't a multiple of 64px, LOD1
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* and LOD2+ will share CCS elements.
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*/
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return false;
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}
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}
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/* Wa_18020603990 - slow clear surfaces up to 256x256, 32bpp. */
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